1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17allOf:
18  - $ref: /schemas/pci/snps,dw-pcie.yaml#
19
20properties:
21  compatible:
22    enum:
23      - fsl,imx6q-pcie
24      - fsl,imx6sx-pcie
25      - fsl,imx6qp-pcie
26      - fsl,imx7d-pcie
27      - fsl,imx8mq-pcie
28      - fsl,imx8mm-pcie
29
30  reg:
31    items:
32      - description: Data Bus Interface (DBI) registers.
33      - description: PCIe configuration space region.
34
35  reg-names:
36    items:
37      - const: dbi
38      - const: config
39
40  interrupts:
41    items:
42      - description: builtin MSI controller.
43
44  interrupt-names:
45    items:
46      - const: msi
47
48  clocks:
49    minItems: 3
50    items:
51      - description: PCIe bridge clock.
52      - description: PCIe bus clock.
53      - description: PCIe PHY clock.
54      - description: Additional required clock entry for imx6sx-pcie,
55          imx8mq-pcie.
56
57  clock-names:
58    minItems: 3
59    items:
60      - const: pcie
61      - const: pcie_bus
62      - const: pcie_phy
63      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
64
65  num-lanes:
66    const: 1
67
68  fsl,imx7d-pcie-phy:
69    $ref: /schemas/types.yaml#/definitions/phandle
70    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
71      required properties for imx7d-pcie and imx8mq-pcie.
72
73  power-domains:
74    items:
75      - description: The phandle pointing to the DISPLAY domain for
76          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
77          imx8mq-pcie.
78      - description: The phandle pointing to the PCIE_PHY power domains
79          for imx6sx-pcie.
80
81  power-domain-names:
82    items:
83      - const: pcie
84      - const: pcie_phy
85
86  resets:
87    maxItems: 3
88    description: Phandles to PCIe-related reset lines exposed by SRC
89      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
90
91  reset-names:
92    items:
93      - const: pciephy
94      - const: apps
95      - const: turnoff
96
97  fsl,tx-deemph-gen1:
98    description: Gen1 De-emphasis value (optional required).
99    $ref: /schemas/types.yaml#/definitions/uint32
100    default: 0
101
102  fsl,tx-deemph-gen2-3p5db:
103    description: Gen2 (3.5db) De-emphasis value (optional required).
104    $ref: /schemas/types.yaml#/definitions/uint32
105    default: 0
106
107  fsl,tx-deemph-gen2-6db:
108    description: Gen2 (6db) De-emphasis value (optional required).
109    $ref: /schemas/types.yaml#/definitions/uint32
110    default: 20
111
112  fsl,tx-swing-full:
113    description: Gen2 TX SWING FULL value (optional required).
114    $ref: /schemas/types.yaml#/definitions/uint32
115    default: 127
116
117  fsl,tx-swing-low:
118    description: TX launch amplitude swing_low value (optional required).
119    $ref: /schemas/types.yaml#/definitions/uint32
120    default: 127
121
122  fsl,max-link-speed:
123    description: Specify PCI Gen for link capability (optional required).
124      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
125      requirements and thus for gen2 capability a gen2 compliant clock
126      generator should be used and configured.
127    $ref: /schemas/types.yaml#/definitions/uint32
128    enum: [1, 2, 3, 4]
129    default: 1
130
131  phys:
132    maxItems: 1
133
134  phy-names:
135    const: pcie-phy
136
137  reset-gpio:
138    description: Should specify the GPIO for controlling the PCI bus device
139      reset signal. It's not polarity aware and defaults to active-low reset
140      sequence (L=reset state, H=operation state) (optional required).
141
142  reset-gpio-active-high:
143    description: If present then the reset sequence using the GPIO
144      specified in the "reset-gpio" property is reversed (H=reset state,
145      L=operation state) (optional required).
146
147  vpcie-supply:
148    description: Should specify the regulator in charge of PCIe port power.
149      The regulator will be enabled when initializing the PCIe host and
150      disabled either as part of the init process or when shutting down
151      the host (optional required).
152
153  vph-supply:
154    description: Should specify the regulator in charge of VPH one of
155      the three PCIe PHY powers. This regulator can be supplied by both
156      1.8v and 3.3v voltage supplies (optional required).
157
158required:
159  - compatible
160  - reg
161  - reg-names
162  - "#address-cells"
163  - "#size-cells"
164  - device_type
165  - bus-range
166  - ranges
167  - num-lanes
168  - interrupts
169  - interrupt-names
170  - "#interrupt-cells"
171  - interrupt-map-mask
172  - interrupt-map
173  - clocks
174  - clock-names
175
176unevaluatedProperties: false
177
178examples:
179  - |
180    #include <dt-bindings/clock/imx6qdl-clock.h>
181    #include <dt-bindings/interrupt-controller/arm-gic.h>
182
183    pcie: pcie@1ffc000 {
184        compatible = "fsl,imx6q-pcie";
185        reg = <0x01ffc000 0x04000>,
186              <0x01f00000 0x80000>;
187        reg-names = "dbi", "config";
188        #address-cells = <3>;
189        #size-cells = <2>;
190        device_type = "pci";
191        bus-range = <0x00 0xff>;
192        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
193                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
194        num-lanes = <1>;
195        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
196        interrupt-names = "msi";
197        #interrupt-cells = <1>;
198        interrupt-map-mask = <0 0 0 0x7>;
199        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
200                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
201                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
202                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
203        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
204                <&clks IMX6QDL_CLK_LVDS1_GATE>,
205                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
206        clock-names = "pcie", "pcie_bus", "pcie_phy";
207    };
208...
209