| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 47 .tFAW = 50000,
68 .tFAW = 50000,
89 .tFAW = 50000,
110 .tFAW = 50000,
131 .tFAW = 8
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| H A D | of_memory.c | 48 ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); in of_get_min_tck()
80 ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); in of_do_get_timings()
190 ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW); in of_lpddr3_get_min_tck()
233 ret |= of_property_read_u32(np, "tFAW", &tim->tFAW); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 161 u32 tFAW; member
184 u32 tFAW; member
243 u32 tFAW; member
272 u32 tFAW; member
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 22 tFAW-min-tck = <8>;
38 tFAW = <50000>;
60 tFAW = <50000>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 43 .tFAW = 50
67 .tFAW = 50
89 .tFAW = 8
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| H A D | sdram_elpida.c | 210 .tFAW = 50
233 .tFAW = 50
256 .tFAW = 50
271 .tFAW = 8
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 120 tFAW-min-tck:
161 tFAW-min-tck = <8>;
177 tFAW = <50000>;
198 tFAW = <50000>;
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| H A D | jedec,lpddr3.yaml | 62 tFAW-min-tck:
201 tFAW-min-tck = <5>;
226 tFAW = <25000>;
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| H A D | jedec,lpddr2-timings.yaml | 43 tFAW:
122 tFAW = <50000>;
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| H A D | jedec,lpddr3-timings.yaml | 44 tFAW:
140 tFAW = <25000>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 44 .tFAW = 50
66 .tFAW = 8
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| /openbmc/u-boot/board/technologic/ts4600/ |
| H A D | iomux.c | 111 #define TFAW 0xb macro
114 #define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL)
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
54 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 11 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params() local
53 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
57 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 999 u8 twl, txp, tfaw, tcl; in mx6_lpddr2_cfg() local
1044 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1046 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1086 debug("tfaw=%d\n", tfaw); in mx6_lpddr2_cfg()
1141 (tfaw << 4) | tcl; in mx6_lpddr2_cfg()
1229 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1304 tfaw = DIV_ROUND_UP(40000, clkper) - 1; in mx6_ddr3_cfg()
1307 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1315 tfaw = DIV_ROUND_UP(37500, clkper) - 1; in mx6_ddr3_cfg()
1318 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 87 - fsp,dimm-tfaw
150 fsp,dimm-tfaw = <0x14>;
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 23 u8 tfaw; member
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 93 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
145 tfaw = max(ns_to_t(50), 4); in auto_set_timing_para()
170 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| H A D | dram_sun9i.c | 131 u32 tFAW; /* in ps */ member
391 const u32 tFAW = PS2CYCLES_ROUNDUP(para->tFAW); in mctl_channel_init() local
533 writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) | in mctl_channel_init()
644 writel((tMRD << 0) | ((tMOD - 12) << 2) | (tFAW << 5) | in mctl_channel_init()
901 .tFAW = 40, in sunxi_dram_init()
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| H A D | dram_sun8i_a33.c | 93 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
138 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| /openbmc/u-boot/arch/x86/include/asm/arch-baytrail/fsp/ |
| H A D | fsp_vpd.h | 27 uint8_t dimm_tfaw; /* tFAW in DRAM clk */
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 523 * The controller can represent tFAW as 4x, 5x or 6x tRRD only. in pctl_calc_timings()
524 * We want to use the smallest multiplier that satisfies the tFAW in pctl_calc_timings()
526 * tRRD to allow us to operate on a 6x multiplier for tFAW. in pctl_calc_timings()
528 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */ in pctl_calc_timings()
530 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */ in pctl_calc_timings()
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra20/ |
| H A D | emc.h | 51 u32 tfaw; /* 0x98: EMC_TFAW */ member
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | lpddr2.h | 39 …A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=…
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