1*67337e68SIcenowy Zheng #include <common.h>
2*67337e68SIcenowy Zheng #include <asm/arch/dram.h>
3*67337e68SIcenowy Zheng #include <asm/arch/cpu.h>
4*67337e68SIcenowy Zheng
mctl_set_timing_params(uint16_t socid,struct dram_para * para)5*67337e68SIcenowy Zheng void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
6*67337e68SIcenowy Zheng {
7*67337e68SIcenowy Zheng struct sunxi_mctl_ctl_reg * const mctl_ctl =
8*67337e68SIcenowy Zheng (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
9*67337e68SIcenowy Zheng
10*67337e68SIcenowy Zheng u8 tccd = 1;
11*67337e68SIcenowy Zheng u8 tfaw = ns_to_t(50);
12*67337e68SIcenowy Zheng u8 trrd = max(ns_to_t(10), 2);
13*67337e68SIcenowy Zheng u8 trcd = ns_to_t(20);
14*67337e68SIcenowy Zheng u8 trc = ns_to_t(65);
15*67337e68SIcenowy Zheng u8 txp = 2;
16*67337e68SIcenowy Zheng u8 twtr = max(ns_to_t(8), 2);
17*67337e68SIcenowy Zheng u8 trtp = max(ns_to_t(8), 2);
18*67337e68SIcenowy Zheng u8 twr = max(ns_to_t(15), 3);
19*67337e68SIcenowy Zheng u8 trp = ns_to_t(15);
20*67337e68SIcenowy Zheng u8 tras = ns_to_t(45);
21*67337e68SIcenowy Zheng u16 trefi = ns_to_t(7800) / 32;
22*67337e68SIcenowy Zheng u16 trfc = ns_to_t(328);
23*67337e68SIcenowy Zheng
24*67337e68SIcenowy Zheng u8 tmrw = 0;
25*67337e68SIcenowy Zheng u8 tmrd = 2;
26*67337e68SIcenowy Zheng u8 tmod = 12;
27*67337e68SIcenowy Zheng u8 tcke = 3;
28*67337e68SIcenowy Zheng u8 tcksrx = 5;
29*67337e68SIcenowy Zheng u8 tcksre = 5;
30*67337e68SIcenowy Zheng u8 tckesr = 4;
31*67337e68SIcenowy Zheng u8 trasmax = 27;
32*67337e68SIcenowy Zheng
33*67337e68SIcenowy Zheng u8 tcl = 3; /* CL 6 */
34*67337e68SIcenowy Zheng u8 tcwl = 3; /* CWL 6 */
35*67337e68SIcenowy Zheng u8 t_rdata_en = 1;
36*67337e68SIcenowy Zheng u8 wr_latency = 1;
37*67337e68SIcenowy Zheng
38*67337e68SIcenowy Zheng u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */
39*67337e68SIcenowy Zheng u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */
40*67337e68SIcenowy Zheng u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
41*67337e68SIcenowy Zheng u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
42*67337e68SIcenowy Zheng
43*67337e68SIcenowy Zheng u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44*67337e68SIcenowy Zheng u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45*67337e68SIcenowy Zheng u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
46*67337e68SIcenowy Zheng
47*67337e68SIcenowy Zheng /* set mode register */
48*67337e68SIcenowy Zheng writel(0x263, &mctl_ctl->mr[0]);
49*67337e68SIcenowy Zheng writel(0x4, &mctl_ctl->mr[1]);
50*67337e68SIcenowy Zheng writel(0x0, &mctl_ctl->mr[2]);
51*67337e68SIcenowy Zheng writel(0x0, &mctl_ctl->mr[3]);
52*67337e68SIcenowy Zheng
53*67337e68SIcenowy Zheng /* set DRAM timing */
54*67337e68SIcenowy Zheng writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
55*67337e68SIcenowy Zheng DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
56*67337e68SIcenowy Zheng &mctl_ctl->dramtmg[0]);
57*67337e68SIcenowy Zheng writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
58*67337e68SIcenowy Zheng &mctl_ctl->dramtmg[1]);
59*67337e68SIcenowy Zheng writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
60*67337e68SIcenowy Zheng DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
61*67337e68SIcenowy Zheng &mctl_ctl->dramtmg[2]);
62*67337e68SIcenowy Zheng writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
63*67337e68SIcenowy Zheng &mctl_ctl->dramtmg[3]);
64*67337e68SIcenowy Zheng writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
65*67337e68SIcenowy Zheng DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
66*67337e68SIcenowy Zheng writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
67*67337e68SIcenowy Zheng DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
68*67337e68SIcenowy Zheng &mctl_ctl->dramtmg[5]);
69*67337e68SIcenowy Zheng
70*67337e68SIcenowy Zheng /* set two rank timing */
71*67337e68SIcenowy Zheng clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
72*67337e68SIcenowy Zheng (0x66 << 8) | (0x10 << 0));
73*67337e68SIcenowy Zheng
74*67337e68SIcenowy Zheng /* set PHY interface timing, write latency and read latency configure */
75*67337e68SIcenowy Zheng writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
76*67337e68SIcenowy Zheng (wr_latency << 0), &mctl_ctl->pitmg[0]);
77*67337e68SIcenowy Zheng
78*67337e68SIcenowy Zheng /* set PHY timing, PTR0-2 use default */
79*67337e68SIcenowy Zheng writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
80*67337e68SIcenowy Zheng writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
81*67337e68SIcenowy Zheng
82*67337e68SIcenowy Zheng /* set refresh timing */
83*67337e68SIcenowy Zheng writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
84*67337e68SIcenowy Zheng }
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