1*f6457ce5SIcenowy Zheng #include <common.h>
2*f6457ce5SIcenowy Zheng #include <asm/arch/dram.h>
3*f6457ce5SIcenowy Zheng #include <asm/arch/cpu.h>
4*f6457ce5SIcenowy Zheng
mctl_set_timing_params(uint16_t socid,struct dram_para * para)5*f6457ce5SIcenowy Zheng void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
6*f6457ce5SIcenowy Zheng {
7*f6457ce5SIcenowy Zheng struct sunxi_mctl_ctl_reg * const mctl_ctl =
8*f6457ce5SIcenowy Zheng (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
9*f6457ce5SIcenowy Zheng
10*f6457ce5SIcenowy Zheng u8 tccd = 2;
11*f6457ce5SIcenowy Zheng u8 tfaw = ns_to_t(50);
12*f6457ce5SIcenowy Zheng u8 trrd = max(ns_to_t(10), 4);
13*f6457ce5SIcenowy Zheng u8 trcd = ns_to_t(15);
14*f6457ce5SIcenowy Zheng u8 trc = ns_to_t(53);
15*f6457ce5SIcenowy Zheng u8 txp = max(ns_to_t(8), 3);
16*f6457ce5SIcenowy Zheng u8 twtr = max(ns_to_t(8), 4);
17*f6457ce5SIcenowy Zheng u8 trtp = max(ns_to_t(8), 4);
18*f6457ce5SIcenowy Zheng u8 twr = max(ns_to_t(15), 3);
19*f6457ce5SIcenowy Zheng u8 trp = ns_to_t(15);
20*f6457ce5SIcenowy Zheng u8 tras = ns_to_t(38);
21*f6457ce5SIcenowy Zheng u16 trefi = ns_to_t(7800) / 32;
22*f6457ce5SIcenowy Zheng u16 trfc = ns_to_t(350);
23*f6457ce5SIcenowy Zheng
24*f6457ce5SIcenowy Zheng u8 tmrw = 0;
25*f6457ce5SIcenowy Zheng u8 tmrd = 4;
26*f6457ce5SIcenowy Zheng u8 tmod = 12;
27*f6457ce5SIcenowy Zheng u8 tcke = 3;
28*f6457ce5SIcenowy Zheng u8 tcksrx = 5;
29*f6457ce5SIcenowy Zheng u8 tcksre = 5;
30*f6457ce5SIcenowy Zheng u8 tckesr = 4;
31*f6457ce5SIcenowy Zheng u8 trasmax = 24;
32*f6457ce5SIcenowy Zheng
33*f6457ce5SIcenowy Zheng u8 tcl = 6; /* CL 12 */
34*f6457ce5SIcenowy Zheng u8 tcwl = 4; /* CWL 8 */
35*f6457ce5SIcenowy Zheng u8 t_rdata_en = 4;
36*f6457ce5SIcenowy Zheng u8 wr_latency = 2;
37*f6457ce5SIcenowy Zheng
38*f6457ce5SIcenowy Zheng u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
39*f6457ce5SIcenowy Zheng u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
40*f6457ce5SIcenowy Zheng u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
41*f6457ce5SIcenowy Zheng u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
42*f6457ce5SIcenowy Zheng
43*f6457ce5SIcenowy Zheng u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
44*f6457ce5SIcenowy Zheng u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
45*f6457ce5SIcenowy Zheng u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
46*f6457ce5SIcenowy Zheng
47*f6457ce5SIcenowy Zheng /* set mode register */
48*f6457ce5SIcenowy Zheng writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
49*f6457ce5SIcenowy Zheng writel(0x40, &mctl_ctl->mr[1]);
50*f6457ce5SIcenowy Zheng writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
51*f6457ce5SIcenowy Zheng writel(0x0, &mctl_ctl->mr[3]);
52*f6457ce5SIcenowy Zheng
53*f6457ce5SIcenowy Zheng if (socid == SOCID_R40)
54*f6457ce5SIcenowy Zheng writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */
55*f6457ce5SIcenowy Zheng
56*f6457ce5SIcenowy Zheng /* set DRAM timing */
57*f6457ce5SIcenowy Zheng writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
58*f6457ce5SIcenowy Zheng DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
59*f6457ce5SIcenowy Zheng &mctl_ctl->dramtmg[0]);
60*f6457ce5SIcenowy Zheng writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
61*f6457ce5SIcenowy Zheng &mctl_ctl->dramtmg[1]);
62*f6457ce5SIcenowy Zheng writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
63*f6457ce5SIcenowy Zheng DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
64*f6457ce5SIcenowy Zheng &mctl_ctl->dramtmg[2]);
65*f6457ce5SIcenowy Zheng writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
66*f6457ce5SIcenowy Zheng &mctl_ctl->dramtmg[3]);
67*f6457ce5SIcenowy Zheng writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
68*f6457ce5SIcenowy Zheng DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
69*f6457ce5SIcenowy Zheng writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
70*f6457ce5SIcenowy Zheng DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
71*f6457ce5SIcenowy Zheng &mctl_ctl->dramtmg[5]);
72*f6457ce5SIcenowy Zheng
73*f6457ce5SIcenowy Zheng /* set two rank timing */
74*f6457ce5SIcenowy Zheng clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
75*f6457ce5SIcenowy Zheng ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
76*f6457ce5SIcenowy Zheng
77*f6457ce5SIcenowy Zheng /* set PHY interface timing, write latency and read latency configure */
78*f6457ce5SIcenowy Zheng writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
79*f6457ce5SIcenowy Zheng (wr_latency << 0), &mctl_ctl->pitmg[0]);
80*f6457ce5SIcenowy Zheng
81*f6457ce5SIcenowy Zheng /* set PHY timing, PTR0-2 use default */
82*f6457ce5SIcenowy Zheng writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
83*f6457ce5SIcenowy Zheng writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
84*f6457ce5SIcenowy Zheng
85*f6457ce5SIcenowy Zheng /* set refresh timing */
86*f6457ce5SIcenowy Zheng writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
87*f6457ce5SIcenowy Zheng }
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