Home
last modified time | relevance | path

Searched refs:val32 (Results 1 – 25 of 122) sorted by relevance

12345

/openbmc/linux/drivers/edac/
H A Damd8131_edac.c27 static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) in edac_pci_read_dword() argument
31 ret = pci_read_config_dword(dev, reg, val32); in edac_pci_read_dword()
37 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) in edac_pci_write_dword() argument
41 ret = pci_write_config_dword(dev, reg, val32); in edac_pci_write_dword()
74 u32 val32; in amd8131_pcix_init() local
78 edac_pci_read_dword(dev, REG_MEM_LIM, &val32); in amd8131_pcix_init()
79 if (val32 & MEM_LIMIT_MASK) in amd8131_pcix_init()
80 edac_pci_write_dword(dev, REG_MEM_LIM, val32); in amd8131_pcix_init()
83 edac_pci_read_dword(dev, REG_INT_CTLR, &val32); in amd8131_pcix_init()
84 if (val32 & INT_CTLR_DTS) in amd8131_pcix_init()
[all …]
H A Damd8111_edac.c37 static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) in edac_pci_read_dword() argument
41 ret = pci_read_config_dword(dev, reg, val32); in edac_pci_read_dword()
59 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) in edac_pci_write_dword() argument
63 ret = pci_write_config_dword(dev, reg, val32); in edac_pci_write_dword()
87 u32 val32; in amd8111_pci_bridge_init() local
93 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32); in amd8111_pci_bridge_init()
94 if (val32 & PCI_STSCMD_CLEAR_MASK) in amd8111_pci_bridge_init()
95 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32); in amd8111_pci_bridge_init()
98 edac_pci_read_dword(dev, REG_HT_LINK, &val32); in amd8111_pci_bridge_init()
99 if (val32 & HT_LINK_CLEAR_MASK) in amd8111_pci_bridge_init()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8188f.c376 u32 val32, ofdm, mcs; in rtl8188f_set_tx_power() local
384 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8188f_set_tx_power()
385 val32 &= 0xffff00ff; in rtl8188f_set_tx_power()
386 val32 |= (cck << 8); in rtl8188f_set_tx_power()
387 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8188f_set_tx_power()
389 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8188f_set_tx_power()
390 val32 &= 0xff; in rtl8188f_set_tx_power()
391 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8188f_set_tx_power()
392 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8188f_set_tx_power()
446 u32 val32, initial_gain, reg948; in rtl8188f_spur_calibration() local
[all …]
H A Drtl8xxxu_8710b.c482 u32 val32, value = 0xffffffff; in rtl8710b_indirect_read32() local
497 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); in rtl8710b_indirect_read32()
498 while ((val32 & BIT(31)) && (--polling_count > 0)); in rtl8710b_indirect_read32()
502 __func__, addr, val32); in rtl8710b_indirect_read32()
518 u32 val32; in rtl8710b_indirect_write32() local
533 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); in rtl8710b_indirect_write32()
534 while ((val32 & BIT(31)) && (--polling_count > 0)); in rtl8710b_indirect_write32()
538 __func__, val, addr, val32); in rtl8710b_indirect_write32()
558 u32 val32; in rtl8710b_read_efuse8() local
567 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); in rtl8710b_read_efuse8()
[all …]
H A Drtl8xxxu_8723b.c310 u32 val32, sys_cfg, vendor; in rtl8723bu_identify_chip() local
327 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723bu_identify_chip()
328 if (val32 & MULTI_WIFI_FUNC_EN) in rtl8723bu_identify_chip()
330 if (val32 & MULTI_BT_FUNC_EN) in rtl8723bu_identify_chip()
332 if (val32 & MULTI_GPS_FUNC_EN) in rtl8723bu_identify_chip()
339 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723bu_identify_chip()
340 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723bu_identify_chip()
407 u32 val32, ofdm, mcs; in rtl8723b_set_tx_power() local
415 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
416 val32 &= 0xffff00ff; in rtl8723b_set_tx_power()
[all …]
H A Drtl8xxxu_8192e.c484 u32 val32, bonding, sys_cfg, vendor; in rtl8192eu_identify_chip() local
513 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
514 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
531 u32 val32, ofdm, mcs; in rtl8192e_set_tx_power() local
540 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
541 val32 &= 0xffff00ff; in rtl8192e_set_tx_power()
542 val32 |= (cck << 8); in rtl8192e_set_tx_power()
543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
546 val32 &= 0xff; in rtl8192e_set_tx_power()
[all …]
H A Drtl8xxxu_core.c712 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_read32()
714 data = le32_to_cpu(priv->usb_buf.val32); in rtl8xxxu_read32()
777 priv->usb_buf.val32 = cpu_to_le32(val); in rtl8xxxu_write32()
780 addr, 0, &priv->usb_buf.val32, sizeof(u32), in rtl8xxxu_write32()
828 u32 val32; in rtl8xxxu_write32_set() local
830 val32 = rtl8xxxu_read32(priv, addr); in rtl8xxxu_write32_set()
831 val32 |= bits; in rtl8xxxu_write32_set()
832 return rtl8xxxu_write32(priv, addr, val32); in rtl8xxxu_write32_set()
837 u32 val32; in rtl8xxxu_write32_clear() local
839 val32 = rtl8xxxu_read32(priv, addr); in rtl8xxxu_write32_clear()
[all …]
H A Drtl8xxxu_8188e.c442 u32 val32, rsr; in rtl8188eu_config_channel() local
457 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
458 val32 &= ~FPGA_RF_MODE; in rtl8188eu_config_channel()
459 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
461 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188eu_config_channel()
462 val32 &= ~FPGA_RF_MODE; in rtl8188eu_config_channel()
463 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188eu_config_channel()
484 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
485 val32 |= FPGA_RF_MODE; in rtl8188eu_config_channel()
486 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
[all …]
H A Drtl8xxxu_8723a.c135 u32 val32, sys_cfg, vendor; in rtl8723au_identify_chip() local
154 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723au_identify_chip()
155 if (val32 & MULTI_WIFI_FUNC_EN) in rtl8723au_identify_chip()
157 if (val32 & MULTI_BT_FUNC_EN) in rtl8723au_identify_chip()
159 if (val32 & MULTI_GPS_FUNC_EN) in rtl8723au_identify_chip()
166 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723au_identify_chip()
167 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723au_identify_chip()
270 u32 val32; in rtl8723a_emu_to_active() local
297 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723a_emu_to_active()
298 if (val32 & BIT(17)) in rtl8723a_emu_to_active()
[all …]
H A Drtl8xxxu_8192f.c411 u32 sys_cfg, vendor, val32; in rtl8192fu_identify_chip() local
426 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8192fu_identify_chip()
427 priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); in rtl8192fu_identify_chip()
428 priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); in rtl8192fu_identify_chip()
429 priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); in rtl8192fu_identify_chip()
435 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192fu_identify_chip()
436 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192fu_identify_chip()
445 u32 val32, ofdm, mcs; in rtl8192f_set_tx_power() local
454 val32 = (cck << 16) | (cck << 8) | cck; in rtl8192f_set_tx_power()
456 0x7f7f7f00, val32); in rtl8192f_set_tx_power()
[all …]
/openbmc/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw_20_comp.h25 u32 val32 = 0; in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() local
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
[all …]
/openbmc/linux/drivers/watchdog/
H A DiTCO_vendor_support.c79 unsigned long val32; in supermicro_old_pre_start() local
82 val32 = inl(smires->start); in supermicro_old_pre_start()
83 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ in supermicro_old_pre_start()
84 outl(val32, smires->start); /* Needed to activate watchdog */ in supermicro_old_pre_start()
89 unsigned long val32; in supermicro_old_pre_stop() local
92 val32 = inl(smires->start); in supermicro_old_pre_stop()
93 val32 |= 0x00002000; /* Turn on SMI clearing watchdog */ in supermicro_old_pre_stop()
94 outl(val32, smires->start); /* Needed to deactivate watchdog */ in supermicro_old_pre_stop()
130 unsigned long val32; in broken_bios_start() local
132 val32 = inl(smires->start); in broken_bios_start()
[all …]
/openbmc/linux/drivers/net/wireless/st/cw1200/
H A Dfwio.c55 u32 val32; in cw1200_load_firmware_cw1200() local
136 REG_READ(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
137 val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT; in cw1200_load_firmware_cw1200()
138 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
141 val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT; in cw1200_load_firmware_cw1200()
142 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32); in cw1200_load_firmware_cw1200()
160 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32); in cw1200_load_firmware_cw1200()
161 if (val32 == DOWNLOAD_I_AM_HERE) in cw1200_load_firmware_cw1200()
166 if (val32 != DOWNLOAD_I_AM_HERE) { in cw1200_load_firmware_cw1200()
176 val32 = firmware->size; /* Explicit cast from size_t to u32 */ in cw1200_load_firmware_cw1200()
[all …]
H A Dhwio.c174 u32 val32 = 0; in cw1200_indirect_read() local
191 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); in cw1200_indirect_read()
199 val32 | prefetch); in cw1200_indirect_read()
207 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); in cw1200_indirect_read()
212 if (!(val32 & prefetch)) in cw1200_indirect_read()
218 if (val32 & prefetch) { in cw1200_indirect_read()
269 u32 val32; in __cw1200_irq_enable() local
274 ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32); in __cw1200_irq_enable()
281 val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE; in __cw1200_irq_enable()
283 val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE; in __cw1200_irq_enable()
[all …]
/openbmc/u-boot/drivers/ata/
H A Dfsl_sata.c82 u32 val32; in init_sata() local
159 val32 = in_le32(&reg->hcontrol); in init_sata()
160 val32 &= ~HCONTROL_ONOFF; in init_sata()
161 val32 |= HCONTROL_FORCE_OFFLINE; in init_sata()
162 out_le32(&reg->hcontrol, val32); in init_sata()
171 val32 = in_le32(&reg->hcontrol); in init_sata()
172 val32 |= HCONTROL_HDR_SNOOP; in init_sata()
173 out_le32(&reg->hcontrol, val32); in init_sata()
176 val32 = in_le32(&reg->hcontrol); in init_sata()
177 val32 &= ~HCONTROL_INT_EN_ALL; in init_sata()
[all …]
/openbmc/qemu/hw/misc/
H A Dsifive_u_otp.c107 uint32_t val32 = (uint32_t)val64; in sifive_u_otp_write() local
111 s->pa = val32 & SIFIVE_U_OTP_PA_MASK; in sifive_u_otp_write()
114 s->paio = val32; in sifive_u_otp_write()
117 s->pas = val32; in sifive_u_otp_write()
120 s->pce = val32; in sifive_u_otp_write()
123 s->pclk = val32; in sifive_u_otp_write()
126 s->pdin = val32; in sifive_u_otp_write()
132 s->pdstb = val32; in sifive_u_otp_write()
135 s->pprog = val32; in sifive_u_otp_write()
138 s->ptc = val32; in sifive_u_otp_write()
[all …]
H A Dsifive_u_prci.c62 uint32_t val32 = (uint32_t)val64; in sifive_u_prci_write() local
66 s->hfxosccfg = val32; in sifive_u_prci_write()
71 s->corepllcfg0 = val32; in sifive_u_prci_write()
78 s->ddrpllcfg0 = val32; in sifive_u_prci_write()
85 s->ddrpllcfg1 = val32; in sifive_u_prci_write()
88 s->gemgxlpllcfg0 = val32; in sifive_u_prci_write()
95 s->gemgxlpllcfg1 = val32; in sifive_u_prci_write()
98 s->coreclksel = val32; in sifive_u_prci_write()
101 s->devicesreset = val32; in sifive_u_prci_write()
104 s->clkmuxstatus = val32; in sifive_u_prci_write()
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-cfg-afdo.c35 .val32 = 0x20001,
41 .val32 = 0x20002,
53 .val32 = 0,
59 .val32 = 0x10001,
71 .val32 = 1,
77 .val32 = 0x8102,
84 .val32 = 0x0081,
90 .val32 = 0x0000,
96 .val32 = 0x0003,
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Ddebug.c979 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ in rtw89_debug_mac_dump_dle_dbg()
980 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ in rtw89_debug_mac_dump_dle_dbg()
981 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ in rtw89_debug_mac_dump_dle_dbg()
988 u32 val32; in rtw89_debug_mac_dump_dle_dbg() local
2199 u32 val32; in rtw89_debug_mac_dbg_port_sel() local
2220 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); in rtw89_debug_mac_dbg_port_sel()
2221 val32 |= B_AX_SCH_DBG_EN; in rtw89_debug_mac_dbg_port_sel()
2222 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); in rtw89_debug_mac_dbg_port_sel()
2227 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); in rtw89_debug_mac_dbg_port_sel()
2228 val32 |= B_AX_SCH_DBG_EN; in rtw89_debug_mac_dbg_port_sel()
[all …]
/openbmc/linux/arch/riscv/kvm/
H A Daia_aplic.c388 static int aplic_mmio_read_offset(struct kvm *kvm, gpa_t off, u32 *val32) in aplic_mmio_read_offset() argument
397 *val32 = APLIC_DOMAINCFG_RDONLY | in aplic_mmio_read_offset()
402 *val32 = aplic_read_sourcecfg(aplic, i); in aplic_mmio_read_offset()
406 *val32 = aplic_read_pending_word(aplic, i); in aplic_mmio_read_offset()
408 *val32 = 0; in aplic_mmio_read_offset()
412 *val32 = aplic_read_input_word(aplic, i); in aplic_mmio_read_offset()
414 *val32 = 0; in aplic_mmio_read_offset()
418 *val32 = aplic_read_enabled_word(aplic, i); in aplic_mmio_read_offset()
420 *val32 = 0; in aplic_mmio_read_offset()
423 *val32 = 0; in aplic_mmio_read_offset()
[all …]
/openbmc/qemu/hw/ssi/
H A Dibex_spi_host.c347 uint32_t val32 = val64; in ibex_spi_host_write() local
360 if (FIELD_EX32(val32, INTR_STATE, ERROR)) { in ibex_spi_host_write()
363 if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { in ibex_spi_host_write()
369 s->regs[addr] = val32; in ibex_spi_host_write()
372 s->regs[addr] = val32; in ibex_spi_host_write()
376 s->regs[addr] = val32; in ibex_spi_host_write()
381 s->regs[addr] = val32; in ibex_spi_host_write()
383 if (val32 & R_CONTROL_SW_RST_MASK) { in ibex_spi_host_write()
389 if (val32 & R_CONTROL_OUTPUT_EN_MASK) { in ibex_spi_host_write()
396 s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32; in ibex_spi_host_write()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l35.c1246 unsigned int val32 = 0; in cs35l35_handle_of_data() local
1258 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32); in cs35l35_handle_of_data()
1260 if (val32 < 2600 || val32 > 9000) { in cs35l35_handle_of_data()
1262 "Invalid Boost Voltage %d mV\n", val32); in cs35l35_handle_of_data()
1265 pdata->bst_vctl = ((val32 - 2600) / 100) + 1; in cs35l35_handle_of_data()
1268 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32); in cs35l35_handle_of_data()
1270 if (val32 < 1680 || val32 > 4480) { in cs35l35_handle_of_data()
1272 "Invalid Boost Peak Current %u mA\n", val32); in cs35l35_handle_of_data()
1276 pdata->bst_ipk = ((val32 - 1680) / 110) | CS35L35_VALID_PDATA; in cs35l35_handle_of_data()
1279 ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val32); in cs35l35_handle_of_data()
[all …]
H A Dcs35l33.c924 u32 val32; in cs35l33_get_hg_data() local
930 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0) in cs35l33_get_hg_data()
931 hg_config->mem_depth = val32; in cs35l33_get_hg_data()
933 &val32) >= 0) in cs35l33_get_hg_data()
934 hg_config->release_rate = val32; in cs35l33_get_hg_data()
935 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0) in cs35l33_get_hg_data()
936 hg_config->ldo_thld = val32; in cs35l33_get_hg_data()
938 &val32) >= 0) in cs35l33_get_hg_data()
939 hg_config->ldo_path_disable = val32; in cs35l33_get_hg_data()
941 &val32) >= 0) in cs35l33_get_hg_data()
[all …]
/openbmc/qemu/hw/sd/
H A Dcadence_sdhci.c83 uint32_t val32 = (uint32_t)val; in cadence_sdhci_write() local
91 if (val32 & CADENCE_SDHCI_HRS00_SWR) { in cadence_sdhci_write()
101 if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { in cadence_sdhci_write()
102 val32 |= CADENCE_SDHCI_HRS04_ACK; in cadence_sdhci_write()
104 val32 &= ~CADENCE_SDHCI_HRS04_ACK; in cadence_sdhci_write()
107 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
110 if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { in cadence_sdhci_write()
111 val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP; in cadence_sdhci_write()
114 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
117 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
/openbmc/linux/drivers/misc/ocxl/
H A Dconfig.c365 u32 val32; in read_template_version() local
369 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32); in read_template_version()
373 *len = EXTRACT_BITS(val32, 16, 31); in read_template_version()
374 major = EXTRACT_BITS(val32, 8, 15); in read_template_version()
375 minor = EXTRACT_BITS(val32, 0, 7); in read_template_version()
569 u32 val32; in read_afu_lpc_memory_info() local
590 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32); in read_afu_lpc_memory_info()
594 val32 = EXTRACT_BITS(val32, 0, 7); in read_afu_lpc_memory_info()
595 if (!val32) in read_afu_lpc_memory_info()
608 total_mem_size = 1ull << val32; in read_afu_lpc_memory_info()
[all …]

12345