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Searched refs:timing_cfg_0 (Results 1 – 25 of 45) sorted by relevance

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/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c88 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
120 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
152 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
184 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
216 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
248 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
280 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
312 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc86xx_ddr.c52 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen2.c67 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
H A Darm_ddr_gen3.c92 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c29 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
49 __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); in sdram_init()
H A Dddr.c22 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
49 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
/openbmc/u-boot/board/sbc8641d/
H A Dsbc8641d.c110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
141 ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c25 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
52 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dddr.c31 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, in fixed_sdram()
/openbmc/u-boot/board/socrates/
H A Dsdram.c37 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h60 .timing_cfg_0 = 0x91550018,
/openbmc/u-boot/board/mpc8308_p1m/
H A Dsdram.c46 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/openbmc/u-boot/board/gdsys/mpc8308/
H A Dsdram.c51 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/openbmc/u-boot/board/sbc8548/
H A Dddr.c105 out_be32(&ddr->timing_cfg_0, 0x00220802); in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8308rdb/
H A Dsdram.c50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A Dsdram.c67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
H A Dddr.c23 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
/openbmc/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c327 u32 timing_cfg_0; in mpc83xx_sdram_probe() local
585 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | in mpc83xx_sdram_probe()
594 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); in mpc83xx_sdram_probe()
/openbmc/u-boot/board/freescale/mpc832xemds/
H A Dmpc832xemds.c136 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8313erdb/
H A Dsdram.c76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c91 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A Dmpc8641hpcn.c74 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8323erdb/
H A Dmpc8323erdb.c115 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
/openbmc/u-boot/board/freescale/mpc8572ds/
H A Dmpc8572ds.c71 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()

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