1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 25d108ac8SSergei Poselenov /* 35d108ac8SSergei Poselenov * (C) Copyright 2008 45d108ac8SSergei Poselenov * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 55d108ac8SSergei Poselenov */ 65d108ac8SSergei Poselenov 75d108ac8SSergei Poselenov #include <common.h> 85d108ac8SSergei Poselenov #include <asm/processor.h> 95d108ac8SSergei Poselenov #include <asm/immap_85xx.h> 105614e71bSYork Sun #include <fsl_ddr_sdram.h> 115d108ac8SSergei Poselenov #include <asm/processor.h> 125d108ac8SSergei Poselenov #include <asm/mmu.h> 135d108ac8SSergei Poselenov #include <spd_sdram.h> 145d108ac8SSergei Poselenov 155d108ac8SSergei Poselenov 165d108ac8SSergei Poselenov #if !defined(CONFIG_SPD_EEPROM) 175d108ac8SSergei Poselenov /* 185d108ac8SSergei Poselenov * Autodetect onboard DDR SDRAM on 85xx platforms 195d108ac8SSergei Poselenov * 205d108ac8SSergei Poselenov * NOTE: Some of the hardcoded values are hardware dependant, 215d108ac8SSergei Poselenov * so this should be extended for other future boards 225d108ac8SSergei Poselenov * using this routine! 235d108ac8SSergei Poselenov */ fixed_sdram(void)2438dba0c2SBecky Brucephys_size_t fixed_sdram(void) 255d108ac8SSergei Poselenov { 269a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 279a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 285d108ac8SSergei Poselenov 295d108ac8SSergei Poselenov /* 305d108ac8SSergei Poselenov * Disable memory controller. 315d108ac8SSergei Poselenov */ 325d108ac8SSergei Poselenov ddr->cs0_config = 0; 335d108ac8SSergei Poselenov ddr->sdram_cfg = 0; 345d108ac8SSergei Poselenov 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; 376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; 396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; 406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_mode = CONFIG_SYS_DDR_MODE; 416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; 426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; 445d108ac8SSergei Poselenov 455d108ac8SSergei Poselenov asm ("sync;isync;msync"); 465d108ac8SSergei Poselenov udelay(1000); 475d108ac8SSergei Poselenov 486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; 495d108ac8SSergei Poselenov asm ("sync; isync; msync"); 505d108ac8SSergei Poselenov udelay(1000); 515d108ac8SSergei Poselenov 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { 535d108ac8SSergei Poselenov /* 545d108ac8SSergei Poselenov * OK, size detected -> all done 555d108ac8SSergei Poselenov */ 566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD return CONFIG_SYS_SDRAM_SIZE<<20; 575d108ac8SSergei Poselenov } 585d108ac8SSergei Poselenov 595d108ac8SSergei Poselenov return 0; /* nothing found ! */ 605d108ac8SSergei Poselenov } 615d108ac8SSergei Poselenov #endif 625d108ac8SSergei Poselenov 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_DRAM_TEST) testdram(void)645d108ac8SSergei Poselenovint testdram (void) 655d108ac8SSergei Poselenov { 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; 685d108ac8SSergei Poselenov uint *p; 695d108ac8SSergei Poselenov 705d108ac8SSergei Poselenov printf ("SDRAM test phase 1:\n"); 715d108ac8SSergei Poselenov for (p = pstart; p < pend; p++) 725d108ac8SSergei Poselenov *p = 0xaaaaaaaa; 735d108ac8SSergei Poselenov 745d108ac8SSergei Poselenov for (p = pstart; p < pend; p++) { 755d108ac8SSergei Poselenov if (*p != 0xaaaaaaaa) { 765d108ac8SSergei Poselenov printf ("SDRAM test fails at: %08x\n", (uint) p); 775d108ac8SSergei Poselenov return 1; 785d108ac8SSergei Poselenov } 795d108ac8SSergei Poselenov } 805d108ac8SSergei Poselenov 815d108ac8SSergei Poselenov printf ("SDRAM test phase 2:\n"); 825d108ac8SSergei Poselenov for (p = pstart; p < pend; p++) 835d108ac8SSergei Poselenov *p = 0x55555555; 845d108ac8SSergei Poselenov 855d108ac8SSergei Poselenov for (p = pstart; p < pend; p++) { 865d108ac8SSergei Poselenov if (*p != 0x55555555) { 875d108ac8SSergei Poselenov printf ("SDRAM test fails at: %08x\n", (uint) p); 885d108ac8SSergei Poselenov return 1; 895d108ac8SSergei Poselenov } 905d108ac8SSergei Poselenov } 915d108ac8SSergei Poselenov 925d108ac8SSergei Poselenov printf ("SDRAM test passed.\n"); 935d108ac8SSergei Poselenov return 0; 945d108ac8SSergei Poselenov } 955d108ac8SSergei Poselenov #endif 96