1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <fsl_ddr_sdram.h>
9
10 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
11 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
12 #endif
13
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)14 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
15 unsigned int ctrl_num, int step)
16 {
17 unsigned int i;
18 struct ccsr_ddr __iomem *ddr;
19
20 switch (ctrl_num) {
21 case 0:
22 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
23 break;
24 case 1:
25 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
26 break;
27 default:
28 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
29 return;
30 }
31
32 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
33 if (i == 0) {
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs0_config, regs->cs[i].config);
36
37 } else if (i == 1) {
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs1_config, regs->cs[i].config);
40
41 } else if (i == 2) {
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs2_config, regs->cs[i].config);
44
45 } else if (i == 3) {
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
47 out_be32(&ddr->cs3_config, regs->cs[i].config);
48 }
49 }
50
51 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
52 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
53 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
54 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
55 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
56 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
57 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
58 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
59 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
60 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
61 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
62 out_be32(&ddr->init_addr, regs->ddr_init_addr);
63 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
64
65 debug("before go\n");
66
67 /*
68 * 200 painful micro-seconds must elapse between
69 * the DDR clock setup and the DDR config enable.
70 */
71 udelay(200);
72 asm volatile("sync;isync");
73
74 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
75
76 /*
77 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
78 */
79 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
80 udelay(10000); /* throttle polling rate */
81 }
82 }
83