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Searched refs:sctlr_el (Results 1 – 17 of 17) sorted by relevance

/openbmc/qemu/linux-user/aarch64/
H A Dmte_user_helper.c34 env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); in arm_set_mte_tcf0()
H A Dcpu_loop.c208 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs()
210 env->cp15.sctlr_el[i] |= SCTLR_EE; in target_cpu_copy_regs()
H A Dtarget_prctl.h202 ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT; in do_prctl_get_tagged_addr_ctrl()
/openbmc/qemu/hw/arm/
H A Dboot.c701 env->cp15.sctlr_el[1] &= ~SCTLR_E0E; in do_cpu_reset()
703 env->cp15.sctlr_el[i] &= ~SCTLR_EE; in do_cpu_reset()
708 env->cp15.sctlr_el[1] |= SCTLR_E0E; in do_cpu_reset()
710 env->cp15.sctlr_el[i] |= SCTLR_EE; in do_cpu_reset()
715 env->cp15.sctlr_el[1] |= SCTLR_B; in do_cpu_reset()
/openbmc/qemu/linux-user/arm/
H A Dcpu_loop.c532 env->cp15.sctlr_el[1] |= SCTLR_E0E; in target_cpu_copy_regs()
534 env->cp15.sctlr_el[1] |= SCTLR_B; in target_cpu_copy_regs()
H A Dsignal.c207 if (env->cp15.sctlr_el[1] & SCTLR_E0E) { in setup_return()
/openbmc/qemu/target/arm/
H A Dcpu.c268 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; in arm_cpu_reset_hold()
270 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | in arm_cpu_reset_hold()
273 env->cp15.sctlr_el[1] |= SCTLR_BT0; in arm_cpu_reset_hold()
276 env->cp15.sctlr_el[1] |= SCTLR_TIDCP; in arm_cpu_reset_hold()
289 env->cp15.sctlr_el[1] |= SCTLR_EnTP2; in arm_cpu_reset_hold()
308 env->cp15.sctlr_el[1] |= SCTLR_ATA0; in arm_cpu_reset_hold()
323 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; in arm_cpu_reset_hold()
327 env->cp15.sctlr_el[1] |= SCTLR_MSCEN; in arm_cpu_reset_hold()
700 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) { in arm_excp_unmasked()
702 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) && in arm_excp_unmasked()
H A Darch_dump.c439 info->d_endian = (env->cp15.sctlr_el[1] & SCTLR_EE) != 0 in cpu_get_dump_info()
H A Dgdbstub64.c400 tcf0 = extract64(env->cp15.sctlr_el[1], 38, 2); in aarch64_gdb_get_tag_ctl_reg()
H A Dhelper.c5404 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { in aa64_zva_access()
5408 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { in aa64_zva_access()
6444 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
7020 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { in ctr_el0_access()
7024 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { in ctr_el0_access()
8362 if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { in access_scxtnum()
8368 } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { in access_scxtnum()
9387 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), in register_cp_regs_for_features()
11114 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { in take_aarch32_exception()
11122 if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { in take_aarch32_exception()
[all …]
H A Dcpu.h285 uint64_t sctlr_el[4]; member
3021 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
H A Dinternals.h975 return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; in regime_sctlr()
/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c344 if (!(env->cp15.sctlr_el[target_el] & mask)) { in check_wfx_trap()
933 if ((env->cp15.sctlr_el[target_el] & SCTLR_TIDCP) in HELPER()
H A Dhflags.c351 if (env->cp15.sctlr_el[2] & SCTLR_EE) { in rebuild_hflags_a64()
H A Dhelper-a64.c1004 return env->cp15.sctlr_el[1] & SCTLR_MSCEN; in mops_enabled()
1006 return env->cp15.sctlr_el[2] & SCTLR_MSCEN; in mops_enabled()
H A Dmte_helper.c602 sctlr = env->cp15.sctlr_el[reg_el]; in mte_check_fail()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c816 bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; in icv_iar_read()
1302 if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { in icc_iar1_read()