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Searched refs:reg1 (Results 1 – 25 of 210) sorted by relevance

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/openbmc/linux/arch/nios2/include/asm/
H A Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_ptrauth.h26 .macro ptrauth_save_state base, reg1, reg2
27 mrs_s \reg1, SYS_APIAKEYLO_EL1
29 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIAKEYLO_EL1)]
30 mrs_s \reg1, SYS_APIBKEYLO_EL1
32 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APIBKEYLO_EL1)]
33 mrs_s \reg1, SYS_APDAKEYLO_EL1
35 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDAKEYLO_EL1)]
36 mrs_s \reg1, SYS_APDBKEYLO_EL1
38 stp \reg1, \reg2, [\base, #PTRAUTH_REG_OFFSET(CPU_APDBKEYLO_EL1)]
39 mrs_s \reg1, SYS_APGAKEYLO_EL1
[all …]
H A Dkvm_mte.h14 .macro mte_switch_to_guest g_ctxt, h_ctxt, reg1
18 mrs \reg1, hcr_el2
19 tbz \reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@
21 mrs_s \reg1, SYS_RGSR_EL1
22 str \reg1, [\h_ctxt, #CPU_RGSR_EL1]
23 mrs_s \reg1, SYS_GCR_EL1
24 str \reg1, [\h_ctxt, #CPU_GCR_EL1]
26 ldr \reg1, [\g_ctxt, #CPU_RGSR_EL1]
27 msr_s SYS_RGSR_EL1, \reg1
28 ldr \reg1, [\g_ctxt, #CPU_GCR_EL1]
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dap.h74 unsigned long reg1 = 0; in ap_instructions_available() local
84 : [reg1] "+&d" (reg1) in ap_instructions_available()
87 return reg1 != 0; in ap_instructions_available()
135 union ap_queue_status_reg reg1; in ap_tapq() local
144 : [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2) in ap_tapq()
149 return reg1.status; in ap_tapq()
178 union ap_queue_status_reg reg1; in ap_rapq() local
187 : [reg1] "=&d" (reg1.value) in ap_rapq()
190 return reg1.status; in ap_rapq()
203 union ap_queue_status_reg reg1; in ap_zapq() local
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/openbmc/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/openbmc/linux/arch/x86/events/intel/
H A Duncore_nhmex.c353 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_hw_config() local
368 reg1->reg = NHMEX_B0_MSR_MATCH; in nhmex_bbox_hw_config()
370 reg1->reg = NHMEX_B1_MSR_MATCH; in nhmex_bbox_hw_config()
371 reg1->idx = 0; in nhmex_bbox_hw_config()
372 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
380 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_bbox_msr_enable_event() local
383 if (reg1->idx != EXTRA_REG_NONE) { in nhmex_bbox_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
444 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; in nhmex_sbox_hw_config() local
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/openbmc/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2
32 mrs \reg1, cpsr
33 and \reg1, \reg1, #MODE_MASK
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
45 ldr \reg1, [\reg2]
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
47 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
[all …]
/openbmc/linux/arch/arm/lib/
H A Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dcsumpartialcopyuser.S38 .macro load1b, reg1 argument
39 ldrusr \reg1, r0, 1
42 .macro load2b, reg1, reg2
43 ldrusr \reg1, r0, 1
47 .macro load1l, reg1 argument
48 ldrusr \reg1, r0, 4
51 .macro load2l, reg1, reg2
52 ldrusr \reg1, r0, 4
56 .macro load4l, reg1, reg2, reg3, reg4
57 ldrusr \reg1, r0, 4
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/openbmc/linux/crypto/
H A Daria_generic.c32 u32 reg0, reg1, reg2, reg3; in aria_set_encrypt_key() local
44 reg1 = w0[1] ^ ck[1]; in aria_set_encrypt_key()
48 aria_subst_diff_odd(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
68 w1[1] ^= reg1; in aria_set_encrypt_key()
73 reg1 = w1[1]; in aria_set_encrypt_key()
78 reg1 ^= ck[5]; in aria_set_encrypt_key()
82 aria_subst_diff_even(&reg0, &reg1, &reg2, &reg3); in aria_set_encrypt_key()
85 reg1 ^= w0[1]; in aria_set_encrypt_key()
90 w2[1] = reg1; in aria_set_encrypt_key()
95 reg1 ^= ck[9]; in aria_set_encrypt_key()
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/openbmc/linux/sound/pci/ice1712/
H A Dwm8776.c133 .reg1 = WM8776_REG_DACLVOL,
143 .reg1 = WM8776_REG_DACCTRL1,
152 .reg1 = WM8776_REG_DACCTRL1,
159 .reg1 = WM8776_REG_HPLVOL,
170 .reg1 = WM8776_REG_PWRDOWN,
177 .reg1 = WM8776_REG_HPLVOL,
186 .reg1 = WM8776_REG_OUTMUX,
192 .reg1 = WM8776_REG_OUTMUX,
198 .reg1 = WM8776_REG_DACCTRL1,
204 .reg1 = WM8776_REG_PHASESWAP,
[all …]
H A Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
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/openbmc/u-boot/post/lib_powerpc/
H A Drlwimi.c63 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwimi() local
72 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwimi()
73 ASM_LWZ(reg1, stk, 8), in cpu_post_test_rlwimi()
75 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwimi()
76 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwimi()
77 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwimi()
91 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwimi()
92 ASM_LWZ(reg1, stk, 8), in cpu_post_test_rlwimi()
94 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | in cpu_post_test_rlwimi()
96 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwimi()
[all …]
H A Dtwo.c82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_two() local
90 ASM_STW(reg1, stk, 0), in cpu_post_test_two()
92 ASM_11(test->cmd, reg1, reg0), in cpu_post_test_two()
93 ASM_STW(reg1, stk, 8), in cpu_post_test_two()
94 ASM_LWZ(reg1, stk, 0), in cpu_post_test_two()
107 ASM_STW(reg1, stk, 0), in cpu_post_test_two()
109 ASM_11(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_two()
110 ASM_STW(reg1, stk, 8), in cpu_post_test_two()
111 ASM_LWZ(reg1, stk, 0), in cpu_post_test_two()
H A Dsrawi.c62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_srawi() local
70 ASM_STW(reg1, stk, 0), in cpu_post_test_srawi()
72 ASM_11S(test->cmd, reg1, reg0, test->op2), in cpu_post_test_srawi()
73 ASM_STW(reg1, stk, 8), in cpu_post_test_srawi()
74 ASM_LWZ(reg1, stk, 0), in cpu_post_test_srawi()
87 ASM_STW(reg1, stk, 0), in cpu_post_test_srawi()
89 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, in cpu_post_test_srawi()
90 ASM_STW(reg1, stk, 8), in cpu_post_test_srawi()
91 ASM_LWZ(reg1, stk, 0), in cpu_post_test_srawi()
H A Dtwox.c82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_twox() local
90 ASM_STW(reg1, stk, 0), in cpu_post_test_twox()
92 ASM_11X(test->cmd, reg1, reg0), in cpu_post_test_twox()
93 ASM_STW(reg1, stk, 8), in cpu_post_test_twox()
94 ASM_LWZ(reg1, stk, 0), in cpu_post_test_twox()
107 ASM_STW(reg1, stk, 0), in cpu_post_test_twox()
109 ASM_11X(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_twox()
110 ASM_STW(reg1, stk, 8), in cpu_post_test_twox()
111 ASM_LWZ(reg1, stk, 0), in cpu_post_test_twox()
H A Drlwinm.c60 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwinm() local
68 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwinm()
70 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwinm()
71 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwinm()
72 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwinm()
85 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwinm()
87 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, in cpu_post_test_rlwinm()
89 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwinm()
90 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwinm()
H A Dthreex.c126 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threex() local
136 ASM_STW(reg1, stk, 4), in cpu_post_test_threex()
138 ASM_LWZ(reg1, stk, 12), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
143 ASM_LWZ(reg1, stk, 4), in cpu_post_test_threex()
157 ASM_STW(reg1, stk, 4), in cpu_post_test_threex()
159 ASM_LWZ(reg1, stk, 12), in cpu_post_test_threex()
161 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
164 ASM_LWZ(reg1, stk, 4), in cpu_post_test_threex()
H A Drlwnm.c61 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwnm() local
71 ASM_STW(reg1, stk, 4), in cpu_post_test_rlwnm()
73 ASM_LWZ(reg1, stk, 12), in cpu_post_test_rlwnm()
75 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
78 ASM_LWZ(reg1, stk, 4), in cpu_post_test_rlwnm()
92 ASM_STW(reg1, stk, 4), in cpu_post_test_rlwnm()
94 ASM_LWZ(reg1, stk, 12), in cpu_post_test_rlwnm()
96 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
100 ASM_LWZ(reg1, stk, 4), in cpu_post_test_rlwnm()
H A Dthree.c156 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_three() local
166 ASM_STW(reg1, stk, 4), in cpu_post_test_three()
168 ASM_LWZ(reg1, stk, 12), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
173 ASM_LWZ(reg1, stk, 4), in cpu_post_test_three()
187 ASM_STW(reg1, stk, 4), in cpu_post_test_three()
189 ASM_LWZ(reg1, stk, 12), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
194 ASM_LWZ(reg1, stk, 4), in cpu_post_test_three()
/openbmc/u-boot/board/mscc/jr2/
H A Djr2.c38 void __iomem *reg0, *reg1; in vcoreiii_gpio_set_alternate() local
43 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1); in vcoreiii_gpio_set_alternate()
48 reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1); in vcoreiii_gpio_set_alternate()
51 val1 = readl(reg1); in vcoreiii_gpio_set_alternate()
54 writel(val1 & ~mask, reg1); in vcoreiii_gpio_set_alternate()
57 writel(val1 | mask, reg1); in vcoreiii_gpio_set_alternate()
60 writel(val1 | mask, reg1); in vcoreiii_gpio_set_alternate()
63 writel(val1 & ~mask, reg1); in vcoreiii_gpio_set_alternate()
/openbmc/linux/arch/arm64/crypto/
H A Daes-cipher-core.S20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift
23 ubfiz \reg1, \in1e, #2, #8
26 ubfx \reg1, \in1e, #\shift, #8
38 ldr \reg1, [tt, \reg1, uxtw #2]
42 lsl \reg1, \reg1, #2
45 ldrb \reg1, [tt, \reg1, uxtw]
49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift
51 ubfx \reg1, \in1d, #\shift, #8
53 ldr\op \reg1, [tt, \reg1, uxtw #\sz]
/openbmc/linux/drivers/rtc/
H A Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
38 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
40 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
41 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
62 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/openbmc/linux/drivers/media/dvb-frontends/
H A Da8293.c29 u8 reg0, reg1; in a8293_set_voltage_slew() local
125 reg1 = 0x82; in a8293_set_voltage_slew()
126 if (reg1 != dev->reg[1]) { in a8293_set_voltage_slew()
127 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_slew()
130 dev->reg[1] = reg1; in a8293_set_voltage_slew()
148 u8 reg0, reg1; in a8293_set_voltage_noslew() local
178 reg1 = 0x82; in a8293_set_voltage_noslew()
179 if (reg1 != dev->reg[1]) { in a8293_set_voltage_noslew()
180 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage_noslew()
183 dev->reg[1] = reg1; in a8293_set_voltage_noslew()

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