1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2a47a12beSStefan Roese /*
3a47a12beSStefan Roese * (C) Copyright 2002
4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5a47a12beSStefan Roese */
6a47a12beSStefan Roese
7a47a12beSStefan Roese #include <common.h>
8a47a12beSStefan Roese
9a47a12beSStefan Roese /*
10a47a12beSStefan Roese * CPU test
11a47a12beSStefan Roese * Binary instructions instr rD,rA
12a47a12beSStefan Roese *
13a47a12beSStefan Roese * Logic instructions: neg
14a47a12beSStefan Roese * Arithmetic instructions: addme, addze, subfme, subfze
15a47a12beSStefan Roese
16a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and
17a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use
18a47a12beSStefan Roese * different sets of operand registers and result registers.
19a47a12beSStefan Roese */
20a47a12beSStefan Roese
21a47a12beSStefan Roese #include <post.h>
22a47a12beSStefan Roese #include "cpu_asm.h"
23a47a12beSStefan Roese
24a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU
25a47a12beSStefan Roese
26a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
27a47a12beSStefan Roese extern ulong cpu_post_makecr (long v);
28a47a12beSStefan Roese
29a47a12beSStefan Roese static struct cpu_post_two_s
30a47a12beSStefan Roese {
31a47a12beSStefan Roese ulong cmd;
32a47a12beSStefan Roese ulong op;
33a47a12beSStefan Roese ulong res;
34a47a12beSStefan Roese } cpu_post_two_table[] =
35a47a12beSStefan Roese {
36a47a12beSStefan Roese {
37a47a12beSStefan Roese OP_NEG,
38a47a12beSStefan Roese 3,
39a47a12beSStefan Roese -3
40a47a12beSStefan Roese },
41a47a12beSStefan Roese {
42a47a12beSStefan Roese OP_NEG,
43a47a12beSStefan Roese 5,
44a47a12beSStefan Roese -5
45a47a12beSStefan Roese },
46a47a12beSStefan Roese {
47a47a12beSStefan Roese OP_ADDME,
48a47a12beSStefan Roese 6,
49a47a12beSStefan Roese 5
50a47a12beSStefan Roese },
51a47a12beSStefan Roese {
52a47a12beSStefan Roese OP_ADDZE,
53a47a12beSStefan Roese 5,
54a47a12beSStefan Roese 5
55a47a12beSStefan Roese },
56a47a12beSStefan Roese {
57a47a12beSStefan Roese OP_SUBFME,
58a47a12beSStefan Roese 6,
59a47a12beSStefan Roese ~6 - 1
60a47a12beSStefan Roese },
61a47a12beSStefan Roese {
62a47a12beSStefan Roese OP_SUBFZE,
63a47a12beSStefan Roese 5,
64a47a12beSStefan Roese ~5
65a47a12beSStefan Roese },
66a47a12beSStefan Roese };
67d2397817SMike Frysinger static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table);
68a47a12beSStefan Roese
cpu_post_test_two(void)69a47a12beSStefan Roese int cpu_post_test_two (void)
70a47a12beSStefan Roese {
71a47a12beSStefan Roese int ret = 0;
72a47a12beSStefan Roese unsigned int i, reg;
73a47a12beSStefan Roese int flag = disable_interrupts();
74a47a12beSStefan Roese
75a47a12beSStefan Roese for (i = 0; i < cpu_post_two_size && ret == 0; i++)
76a47a12beSStefan Roese {
77a47a12beSStefan Roese struct cpu_post_two_s *test = cpu_post_two_table + i;
78a47a12beSStefan Roese
79a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++)
80a47a12beSStefan Roese {
81a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32;
82a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32;
83a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15;
84a47a12beSStefan Roese unsigned long code[] =
85a47a12beSStefan Roese {
86a47a12beSStefan Roese ASM_STW(stk, 1, -4),
87a47a12beSStefan Roese ASM_ADDI(stk, 1, -16),
88a47a12beSStefan Roese ASM_STW(3, stk, 8),
89a47a12beSStefan Roese ASM_STW(reg0, stk, 4),
90a47a12beSStefan Roese ASM_STW(reg1, stk, 0),
91a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8),
92a47a12beSStefan Roese ASM_11(test->cmd, reg1, reg0),
93a47a12beSStefan Roese ASM_STW(reg1, stk, 8),
94a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0),
95a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4),
96a47a12beSStefan Roese ASM_LWZ(3, stk, 8),
97a47a12beSStefan Roese ASM_ADDI(1, stk, 16),
98a47a12beSStefan Roese ASM_LWZ(stk, 1, -4),
99a47a12beSStefan Roese ASM_BLR,
100a47a12beSStefan Roese };
101a47a12beSStefan Roese unsigned long codecr[] =
102a47a12beSStefan Roese {
103a47a12beSStefan Roese ASM_STW(stk, 1, -4),
104a47a12beSStefan Roese ASM_ADDI(stk, 1, -16),
105a47a12beSStefan Roese ASM_STW(3, stk, 8),
106a47a12beSStefan Roese ASM_STW(reg0, stk, 4),
107a47a12beSStefan Roese ASM_STW(reg1, stk, 0),
108a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8),
109a47a12beSStefan Roese ASM_11(test->cmd, reg1, reg0) | BIT_C,
110a47a12beSStefan Roese ASM_STW(reg1, stk, 8),
111a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0),
112a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4),
113a47a12beSStefan Roese ASM_LWZ(3, stk, 8),
114a47a12beSStefan Roese ASM_ADDI(1, stk, 16),
115a47a12beSStefan Roese ASM_LWZ(stk, 1, -4),
116a47a12beSStefan Roese ASM_BLR,
117a47a12beSStefan Roese };
118a47a12beSStefan Roese ulong res;
119a47a12beSStefan Roese ulong cr;
120a47a12beSStefan Roese
121a47a12beSStefan Roese if (ret == 0)
122a47a12beSStefan Roese {
123a47a12beSStefan Roese cr = 0;
124a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op);
125a47a12beSStefan Roese
126a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1;
127a47a12beSStefan Roese
128a47a12beSStefan Roese if (ret != 0)
129a47a12beSStefan Roese {
130a47a12beSStefan Roese post_log ("Error at two test %d !\n", i);
131a47a12beSStefan Roese }
132a47a12beSStefan Roese }
133a47a12beSStefan Roese
134a47a12beSStefan Roese if (ret == 0)
135a47a12beSStefan Roese {
136a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op);
137a47a12beSStefan Roese
138a47a12beSStefan Roese ret = res == test->res &&
139a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
140a47a12beSStefan Roese
141a47a12beSStefan Roese if (ret != 0)
142a47a12beSStefan Roese {
143a47a12beSStefan Roese post_log ("Error at two test %d !\n", i);
144a47a12beSStefan Roese }
145a47a12beSStefan Roese }
146a47a12beSStefan Roese }
147a47a12beSStefan Roese }
148a47a12beSStefan Roese
149a47a12beSStefan Roese if (flag)
150a47a12beSStefan Roese enable_interrupts();
151a47a12beSStefan Roese
152a47a12beSStefan Roese return ret;
153a47a12beSStefan Roese }
154a47a12beSStefan Roese
155a47a12beSStefan Roese #endif
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