Home
last modified time | relevance | path

Searched refs:readw (Results 1 – 25 of 404) sorted by relevance

12345678910>>...17

/openbmc/linux/drivers/scsi/qla4xxx/
H A Dql4_dbg.c46 readw(&ha->reg->mailbox[i])); in qla4xxx_dump_registers()
51 readw(&ha->reg->flash_address)); in qla4xxx_dump_registers()
54 readw(&ha->reg->flash_data)); in qla4xxx_dump_registers()
57 readw(&ha->reg->ctrl_status)); in qla4xxx_dump_registers()
62 readw(&ha->reg->u1.isp4010.nvram)); in qla4xxx_dump_registers()
66 readw(&ha->reg->u1.isp4022.intr_mask)); in qla4xxx_dump_registers()
69 readw(&ha->reg->u1.isp4022.nvram)); in qla4xxx_dump_registers()
72 readw(&ha->reg->u1.isp4022.semaphore)); in qla4xxx_dump_registers()
76 readw(&ha->reg->req_q_in)); in qla4xxx_dump_registers()
79 readw(&ha->reg->rsp_q_out)); in qla4xxx_dump_registers()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dpl022_spi.c81 if ((readw(ps->base + SSP_PID0) == 0x22) && in pl022_is_supported()
82 (readw(ps->base + SSP_PID1) == 0x10) && in pl022_is_supported()
83 ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) && in pl022_is_supported()
84 (readw(ps->base + SSP_PID3) == 0x00)) in pl022_is_supported()
112 while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) in flush()
113 readw(ps->base + SSP_DR); in flush()
114 } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY); in flush()
124 reg = readw(ps->base + SSP_CR1); in pl022_spi_claim_bus()
142 reg = readw(ps->base + SSP_CR1); in pl022_spi_release_bus()
180 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) { in pl022_spi_xfer()
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-msc313.c55 seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L) in msc313_rtc_read_alarm()
56 | ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16); in msc313_rtc_read_alarm()
60 if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT)) in msc313_rtc_read_alarm()
71 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_alarm_irq_enable()
96 return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT; in msc313_rtc_get_enabled()
103 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_enabled()
117 reg = readw(priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_read_time()
121 while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT) in msc313_rtc_read_time()
124 seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L) in msc313_rtc_read_time()
125 | ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16); in msc313_rtc_read_time()
[all …]
H A Drtc-mxc.c96 day = readw(ioaddr + RTC_DAYR); in get_alarm_or_time()
97 hr_min = readw(ioaddr + RTC_HOURMIN); in get_alarm_or_time()
98 sec = readw(ioaddr + RTC_SECOND); in get_alarm_or_time()
101 day = readw(ioaddr + RTC_DAYALARM); in get_alarm_or_time()
102 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; in get_alarm_or_time()
103 sec = readw(ioaddr + RTC_ALRM_SEC); in get_alarm_or_time()
161 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); in rtc_update_alarm()
174 reg = readw(ioaddr + RTC_RTCIENR); in mxc_rtc_irq_enable()
195 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); in mxc_rtc_interrupt()
264 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; in mxc_rtc_read_alarm()
[all …]
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_udc.c116 w = readw(&musbr->ep[0].ep0.csr0); in musb_db_regs()
125 w = readw(&musbr->frame); in musb_db_regs()
131 w = readw(&musbr->ep[1].epN.rxmaxp); in musb_db_regs()
134 w = readw(&musbr->ep[1].epN.rxcsr); in musb_db_regs()
137 w = readw(&musbr->ep[1].epN.txmaxp); in musb_db_regs()
140 w = readw(&musbr->ep[1].epN.txcsr); in musb_db_regs()
158 readw(&musbr->intrrx); in musb_peri_softconnect()
159 readw(&musbr->intrtx); in musb_peri_softconnect()
209 csr0 = readw(&musbr->ep[0].ep0.csr0); in musb_peri_ep0_stall()
220 csr0 = readw(&musbr->ep[0].ep0.csr0); in musb_peri_ep0_ack_req()
[all …]
H A Dmusb_hcd.c43 csr = readw(&musbr->txcsr); in write_toggle()
58 csr = readw(&musbr->txcsr); in write_toggle()
65 csr = readw(&musbr->rxcsr); in write_toggle()
85 csr = readw(&musbr->txcsr); in check_stall()
93 csr = readw(&musbr->txcsr); in check_stall()
100 csr = readw(&musbr->rxcsr); in check_stall()
122 csr = readw(&musbr->txcsr); in wait_until_ep0_ready()
189 csr = readw(&musbr->txcsr); in wait_until_txep_ready()
221 csr = readw(&musbr->rxcsr); in wait_until_rxep_ready()
251 csr = readw(&musbr->txcsr); in ctrlreq_setup_phase()
[all …]
/openbmc/linux/drivers/scsi/arm/
H A Dcumana_1.c130 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
131 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
132 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
133 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
134 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
135 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
136 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
137 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
/openbmc/linux/drivers/input/keyboard/
H A Dimx_keypad.c94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
113 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
127 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
135 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
259 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
263 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
277 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
281 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
[all …]
/openbmc/u-boot/board/ronetix/pm9263/
H A Dpm9263.c178 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
179 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
184 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
185 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
199 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { in pm9263_lcd_hw_psram_init()
204 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
205 readw(PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
213 if ((readw(PHYS_PSRAM) != 0x1234) in pm9263_lcd_hw_psram_init()
214 || (readw(PHYS_PSRAM + 2) != 0x5678)) in pm9263_lcd_hw_psram_init()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-wmt.c98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy()
149 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
170 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
188 val = readw(i2c_dev->base + REG_CSR); in wmt_i2c_write()
228 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
232 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
237 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
243 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
260 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
[all …]
/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c68 if (!(readw(ctrl_addr) & mask)) in mxc_w1_touch_bit()
74 return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0; in mxc_w1_touch_bit()
93 readw(&regs->tx_rx); in mxc_w1_read_byte()
98 status = readw(&regs->interrupt); in mxc_w1_read_byte()
101 return (u8)readw(&regs->tx_rx); in mxc_w1_read_byte()
119 readw(&regs->tx_rx); in mxc_w1_write_byte()
124 status = readw(&regs->interrupt); in mxc_w1_write_byte()
136 reg_val = readw(&pdata->regs->control); in mxc_w1_reset()
/openbmc/linux/drivers/tty/
H A Dmoxa.c538 while (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
541 if (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
563 ret = readw(ofsAddr + FuncArg); in moxafuncret()
573 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
574 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
575 mask = readw(ofsAddr + RX_mask); in moxa_low_water_check()
774 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
779 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
784 tmp = readw(baseAddr + C320_key); in moxa_load_bios()
787 tmp = readw(baseAddr + C320_status); in moxa_load_bios()
[all …]
/openbmc/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c72 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
95 tmp = readw(&i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_interrupt()
103 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
135 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); in netup_i2c_fifo_tx()
148 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
156 u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f; in netup_i2c_fifo_rx()
172 writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_rx()
180 u16 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_start_xfer()
188 __func__, readw(&i2c->regs->length), in netup_i2c_start_xfer()
189 readw(&i2c->regs->twi_addr_ctrl1), in netup_i2c_start_xfer()
[all …]
H A Dnetup_unidvb_ci.c60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
66 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
91 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_reset()
99 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_ci_slot_reset()
123 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_poll_ci_slot_status()
124 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_poll_ci_slot_status()
/openbmc/u-boot/arch/sh/lib/
H A Dtime_sh2.c23 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
28 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
35 readw(CMCSR_0); in timer_init()
54 ulong data = readw(CMCNT_0); in get_usec()
/openbmc/linux/arch/m68k/coldfire/
H A Dm527x.c59 par = readw(MCFGPIO_PAR_TIMER); in m527x_qspi_init()
87 par = readw(MCFGPIO_PAR_FECI2C); in m527x_i2c_init()
103 sepmask = readw(MCFGPIO_PAR_UART); in m527x_uarts_init()
121 par = readw(MCFGPIO_PAR_FECI2C); in m527x_fec_init()
127 par = readw(MCFGPIO_PAR_FECI2C); in m527x_fec_init()
/openbmc/linux/drivers/pci/
H A Drom.c94 if (readw(image) != 0xAA55) { in pci_get_rom_size()
96 readw(image)); in pci_get_rom_size()
100 pds = image + readw(image + 24); in pci_get_rom_size()
107 length = readw(pds + 16); in pci_get_rom_size()
113 if (readw(image) != 0xAA55) { in pci_get_rom_size()
/openbmc/linux/sound/isa/msnd/
H A Dmsnd_midi.c74 tail = readw(mpu->dev->MIDQ + JQS_wTail); in snd_msndmidi_input_drop()
111 head = readw(mpu->dev->MIDQ + JQS_wHead); in snd_msndmidi_input_read()
112 tail = readw(mpu->dev->MIDQ + JQS_wTail); in snd_msndmidi_input_read()
113 size = readw(mpu->dev->MIDQ + JQS_wSize); in snd_msndmidi_input_read()
117 unsigned char val = readw(pwMIDQData + 2 * head); in snd_msndmidi_input_read()
/openbmc/linux/arch/m68k/include/asm/
H A Dio_no.h65 #define readw readw macro
66 static inline u16 readw(const volatile void __iomem *addr) in readw() function
102 #define readw __raw_readw macro
/openbmc/linux/arch/arm/mach-spear/
H A Dtime.c83 val = readw(gpt_base + CR(CLKSRC)); in spear_clocksource_init()
95 u16 val = readw(gpt_base + CR(CLKEVT)); in spear_timer_shutdown()
116 val = readw(gpt_base + CR(CLKEVT)); in spear_set_oneshot()
135 val = readw(gpt_base + CR(CLKEVT)); in spear_set_periodic()
157 u16 val = readw(gpt_base + CR(CLKEVT)); in clockevent_next_event()
/openbmc/u-boot/board/compulab/common/
H A Domap3_smc911x.c38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
/openbmc/linux/drivers/net/ethernet/packetengines/
H A Dhamachi.c750 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32, in hamachi_init_one()
752 readw(ioaddr + ANLinkPartnerAbility)); in hamachi_init_one()
825 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
830 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
832 return readw(ioaddr + MII_Rd_Data); in mdio_read()
843 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
850 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
891 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6; in hamachi_open()
985 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); in hamachi_open()
1035 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus), in hamachi_timer()
[all …]
/openbmc/linux/drivers/dma/ioat/
H A Ddca.c137 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_add_requester()
163 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_remove_requester()
218 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_count_dca_slots()
270 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat_dca_init()
289 csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); in ioat_dca_init()
295 pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); in ioat_dca_init()
/openbmc/linux/drivers/comedi/drivers/
H A Ddaqboard2000.c311 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in db2k_ai_status()
372 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in db2k_ai_insn_read()
388 status = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_ao_eoc()
470 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS); in db2k_wait_cpld_init()
486 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_wait_cpld_txready()
507 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT)) in db2k_write_cpld()
573 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_load_firmware()
630 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
640 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
674 return readw(dev->mmio + iobase + port * 2); in db2k_8255_cb()
/openbmc/linux/arch/hexagon/include/asm/
H A Dio.h92 static inline u16 readw(const volatile void __iomem *addr) in readw() function
156 #define __raw_readw readw
215 return readw(_IO_BASE + (port & IO_SPACE_LIMIT)); in inw()
326 #define readw readw macro

12345678910>>...17