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Searched refs:phy_read (Results 1 – 25 of 134) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c32 #define phy_read _phy_read macro
60 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
68 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
120 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
129 adv = phy_read(phy, MII_ADVERTISE); in genmii_setup_aneg()
150 adv = phy_read(phy, MII_CTRL1000); in genmii_setup_aneg()
162 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
178 ctl = phy_read(phy, MII_BMCR); in genmii_setup_forced()
211 phy_read(phy, MII_BMSR); in genmii_poll_link()
212 status = phy_read(phy, MII_BMSR); in genmii_poll_link()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dlxt.c66 err = phy_read(phydev, MII_BMSR); in lxt970_ack_interrupt()
71 err = phy_read(phydev, MII_LXT970_ISR); in lxt970_ack_interrupt()
107 irq_status = phy_read(phydev, MII_BMSR); in lxt970_handle_interrupt()
113 irq_status = phy_read(phydev, MII_LXT970_ISR); in lxt970_handle_interrupt()
135 int err = phy_read(phydev, MII_LXT971_ISR); in lxt971_ack_interrupt()
168 irq_status = phy_read(phydev, MII_LXT971_ISR); in lxt971_handle_interrupt()
194 status = phy_read(phydev, MII_BMSR); in lxt973a2_update_link()
199 control = phy_read(phydev, MII_BMCR); in lxt973a2_update_link()
205 status = phy_read(phydev, MII_BMSR); in lxt973a2_update_link()
233 adv = phy_read(phydev, MII_ADVERTISE); in lxt973a2_read_status()
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H A Ddp83tc811.c82 err = phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_ack_interrupt()
86 err = phy_read(phydev, MII_DP83811_INT_STAT2); in dp83811_ack_interrupt()
90 err = phy_read(phydev, MII_DP83811_INT_STAT3); in dp83811_ack_interrupt()
143 phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_set_wol()
204 misr_status = phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_config_intr()
221 misr_status = phy_read(phydev, MII_DP83811_INT_STAT2); in dp83811_config_intr()
236 misr_status = phy_read(phydev, MII_DP83811_INT_STAT3); in dp83811_config_intr()
277 irq_status = phy_read(phydev, MII_DP83811_INT_STAT1); in dp83811_handle_interrupt()
285 irq_status = phy_read(phydev, MII_DP83811_INT_STAT2); in dp83811_handle_interrupt()
293 irq_status = phy_read(phydev, MII_DP83811_INT_STAT3); in dp83811_handle_interrupt()
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H A Dqsemi.c82 err = phy_read(phydev, MII_QS6612_ISR); in qs6612_ack_interrupt()
87 err = phy_read(phydev, MII_BMSR); in qs6612_ack_interrupt()
92 err = phy_read(phydev, MII_EXPANSION); in qs6612_ack_interrupt()
129 irq_status = phy_read(phydev, MII_QS6612_ISR); in qs6612_handle_interrupt()
H A Dmicrochip.c41 rc = phy_read(phydev, LAN88XX_INT_STS); in lan88xx_phy_config_intr()
51 rc = phy_read(phydev, LAN88XX_INT_STS); in lan88xx_phy_config_intr()
61 irq_status = phy_read(phydev, LAN88XX_INT_STS); in lan88xx_handle_interrupt()
313 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL); in lan88xx_set_mdix()
356 temp = phy_read(phydev, LAN88XX_INT_MASK); in lan88xx_link_change_notify()
360 temp = phy_read(phydev, MII_BMCR); in lan88xx_link_change_notify()
367 temp = phy_read(phydev, LAN88XX_INT_STS); in lan88xx_link_change_notify()
370 temp = phy_read(phydev, LAN88XX_INT_MASK); in lan88xx_link_change_notify()
H A Dste10Xp.c35 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
45 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
53 int err = phy_read(phydev, MII_XCIIS); in ste10Xp_ack_interrupt()
88 irq_status = phy_read(phydev, MII_XCIIS); in ste10Xp_handle_interrupt()
H A Dncn26000.c76 ret = phy_read(phydev, MII_BMSR); in ncn26000_read_status()
83 ret = phy_read(phydev, MII_BMSR); in ncn26000_read_status()
108 ret = phy_read(phydev, NCN26000_REG_IRQ_STATUS); in ncn26000_handle_interrupt()
125 ret = phy_read(phydev, NCN26000_REG_IRQ_STATUS); in ncn26000_config_intr()
H A Ddp83848.c56 int err = phy_read(phydev, DP83848_MISR); in dp83848_ack_interrupt()
65 control = phy_read(phydev, DP83848_MICR); in dp83848_config_intr()
98 irq_status = phy_read(phydev, DP83848_MISR); in dp83848_handle_interrupt()
119 val = phy_read(phydev, MII_BMCR); in dp83848_config_init()
H A Dnxp-tja11xx.c147 ret = phy_read(phydev, MII_ECTRL); in tja11xx_wakeup()
353 ret = phy_read(phydev, MII_INTSRC); in tja11xx_config_init()
371 ret = phy_read(phydev, MII_CFG1); in tja11xx_read_status()
381 ret = phy_read(phydev, MII_COMMSTAT); in tja11xx_read_status()
396 ret = phy_read(phydev, MII_COMMSTAT); in tja11xx_get_sqi()
429 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); in tja11xx_get_stats()
447 ret = phy_read(phydev, MII_INTSRC); in tja11xx_hwmon_read()
456 ret = phy_read(phydev, MII_INTSRC); in tja11xx_hwmon_read()
638 ret = phy_read(phydev, MII_PHYSID2); in tja1102_match_phy_device()
665 ret = phy_read(phydev, MII_INTSRC); in tja11xx_ack_interrupt()
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H A Det1011c.c49 int ctl = phy_read(phydev, MII_BMCR); in et1011c_config_aneg()
71 val = phy_read(phydev, ET1011C_STATUS_REG); in et1011c_read_status()
74 val = phy_read(phydev, ET1011C_CONFIG_REG); in et1011c_read_status()
H A Ddp83822.c169 phy_read(phydev, MII_DP83822_MISR2); in dp83822_set_wol()
228 misr_status = phy_read(phydev, MII_DP83822_MISR1); in dp83822_config_intr()
247 misr_status = phy_read(phydev, MII_DP83822_MISR2); in dp83822_config_intr()
266 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); in dp83822_config_intr()
281 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); in dp83822_config_intr()
303 irq_status = phy_read(phydev, MII_DP83822_MISR1); in dp83822_handle_interrupt()
311 irq_status = phy_read(phydev, MII_DP83822_MISR2); in dp83822_handle_interrupt()
337 int status = phy_read(phydev, MII_DP83822_PHYSTS); in dp83822_read_status()
346 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); in dp83822_read_status()
446 bmcr = phy_read(phydev, MII_BMCR); in dp83822_config_init()
H A Dnational.c55 return phy_read(phydev, NS_EXP_MEM_DATA); in ns_exp_read()
66 int ret = phy_read(phydev, DP83865_INT_STATUS); in ns_ack_interrupt()
82 irq_status = phy_read(phydev, DP83865_INT_STATUS); in ns_handle_interrupt()
123 int bmcr = phy_read(phydev, MII_BMCR); in ns_giga_speed_fallback()
H A Damd.c35 err = phy_read(phydev, MII_BMSR); in am79c_ack_interrupt()
39 err = phy_read(phydev, MII_AM79C_IR); in am79c_ack_interrupt()
76 irq_status = phy_read(phydev, MII_AM79C_IR); in am79c_handle_interrupt()
H A DuPD60620.c40 phy_state = phy_read(phydev, MII_BMSR); in upd60620_read_status()
50 phy_state = phy_read(phydev, PHY_PHYSCR); in upd60620_read_status()
64 phy_state = phy_read(phydev, MII_LPA); in upd60620_read_status()
/openbmc/u-boot/drivers/net/phy/
H A Dmarvell.c108 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
112 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
121 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
157 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
175 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
226 reg = phy_read(phydev, in m88e1111s_config()
242 reg = phy_read(phydev, in m88e1111s_config()
257 reg = phy_read(phydev, in m88e1111s_config()
269 reg = phy_read(phydev, in m88e1111s_config()
275 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
[all …]
H A Dvitesse.c90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
150 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
178 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
195 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
198 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
203 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON); in vsc8574_config()
223 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); in vsc8514_config()
238 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
241 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
251 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); in vsc8514_config()
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H A Drealtek.c64 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extread()
69 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in rtl8211f_phy_extread()
78 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extwrite()
120 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
134 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); in rtl8211x_config()
144 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
159 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); in rtl8211f_config()
171 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in rtl8211f_config()
200 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); in rtl8211x_parse_status()
219 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211x_parse_status()
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H A Dgeneric_10g.c40 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
41 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
57 stat2 = phy_read(phydev, mmd, MDIO_STAT2); in gen10g_discover_mmds()
63 devs1 = phy_read(phydev, mmd, MDIO_DEVS1); in gen10g_discover_mmds()
64 devs2 = phy_read(phydev, mmd, MDIO_DEVS2); in gen10g_discover_mmds()
H A Daquantia.c160 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC); in aquantia_load_memory()
262 id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); in aquantia_config()
263 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1); in aquantia_config()
264 fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT); in aquantia_config()
282 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
302 val = phy_read(phydev, MDIO_MMD_PHYXS, in aquantia_config()
332 val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS); in aquantia_config()
333 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID); in aquantia_config()
352 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
353 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
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H A Dphy.c46 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
79 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
91 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
153 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
193 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
228 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
263 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
269 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
291 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_parse_link()
305 gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); in genphy_parse_link()
[all …]
H A Dbroadcom.c44 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
66 reg18 = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm5461_config()
80 reg1c = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD); in bcm5461_config()
97 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
157 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; in bcm5482_read_wirespeed()
165 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
264 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_is_serdes()
300 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_parse_serdes_sr()
H A Dmscc.c662 addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8574_config_pre_init()
665 reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL); in vsc8574_config_pre_init()
865 addr = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_config_pre_init()
868 reg = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_config_pre_init()
1020 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
1034 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
1048 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
1054 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
1075 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); in mscc_parse_status()
1124 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
[all …]
H A Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy.c119 uint16_t phy_read (MAC_ENGINE *eng, int index) in phy_read() function
199 phy_write(eng, adr, ((phy_read(eng, adr) & (~clr_mask)) | set_mask)); in phy_clrset()
210 printf("%02d: %04x ", index, phy_read(eng, index)); in phy_dump()
225 PRINTF(option, "%d:%04x ", 2, phy_read(eng, 2)); in phy_scan_id()
226 PRINTF(option, "%d:%04x ", 3, phy_read(eng, 3)); in phy_scan_id()
256 phy_read(eng, PHY_REG_BMCR), eng->phy.Adr, in phy_basic_setting()
260 phy_read(eng, PHY_REG_BMCR), eng->phy.Adr, in phy_basic_setting()
270 while (phy_read(eng, PHY_REG_BMCR) & 0x8000) { in phy_wait_reset_done()
283 phy_read(eng, PHY_REG_BMCR), eng->phy.Adr, in phy_wait_reset_done()
287 phy_read(eng, PHY_REG_BMCR), eng->phy.Adr, in phy_wait_reset_done()
[all …]
/openbmc/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c62 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
77 scr = phy_read(phydev, MV88E1111_SCR); in mpc8568_fixup_125_clock()
98 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
114 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
119 temp = phy_read(phydev, 30); in mpc8568_mds_phy_fixups()
132 temp = phy_read(phydev, 16); in mpc8568_mds_phy_fixups()

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