15f857575SAndrew Lunn // SPDX-License-Identifier: GPL-2.0
234e45ad9SAndrew F. Davis /*
334e45ad9SAndrew F. Davis * Driver for the Texas Instruments DP83848 PHY
434e45ad9SAndrew F. Davis *
52f67864bSAndrew F. Davis * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
634e45ad9SAndrew F. Davis */
734e45ad9SAndrew F. Davis
834e45ad9SAndrew F. Davis #include <linux/module.h>
934e45ad9SAndrew F. Davis #include <linux/phy.h>
1034e45ad9SAndrew F. Davis
1168336293SAndrew F. Davis #define TI_DP83848C_PHY_ID 0x20005ca0
1293b43fd1SAlvaro G. M #define TI_DP83620_PHY_ID 0x20005ce0
1368336293SAndrew F. Davis #define NS_DP83848C_PHY_ID 0x20005c90
14d1782f7bSAndrew F. Davis #define TLK10X_PHY_ID 0x2000a210
1534e45ad9SAndrew F. Davis
1634e45ad9SAndrew F. Davis /* Registers */
175fed0393SAndrew F. Davis #define DP83848_MICR 0x11 /* MII Interrupt Control Register */
185fed0393SAndrew F. Davis #define DP83848_MISR 0x12 /* MII Interrupt Status Register */
1934e45ad9SAndrew F. Davis
2034e45ad9SAndrew F. Davis /* MICR Register Fields */
2134e45ad9SAndrew F. Davis #define DP83848_MICR_INT_OE BIT(0) /* Interrupt Output Enable */
2234e45ad9SAndrew F. Davis #define DP83848_MICR_INTEN BIT(1) /* Interrupt Enable */
2334e45ad9SAndrew F. Davis
2434e45ad9SAndrew F. Davis /* MISR Register Fields */
2534e45ad9SAndrew F. Davis #define DP83848_MISR_RHF_INT_EN BIT(0) /* Receive Error Counter */
2634e45ad9SAndrew F. Davis #define DP83848_MISR_FHF_INT_EN BIT(1) /* False Carrier Counter */
2734e45ad9SAndrew F. Davis #define DP83848_MISR_ANC_INT_EN BIT(2) /* Auto-negotiation complete */
2834e45ad9SAndrew F. Davis #define DP83848_MISR_DUP_INT_EN BIT(3) /* Duplex Status */
2934e45ad9SAndrew F. Davis #define DP83848_MISR_SPD_INT_EN BIT(4) /* Speed status */
3034e45ad9SAndrew F. Davis #define DP83848_MISR_LINK_INT_EN BIT(5) /* Link status */
3134e45ad9SAndrew F. Davis #define DP83848_MISR_ED_INT_EN BIT(6) /* Energy detect */
3234e45ad9SAndrew F. Davis #define DP83848_MISR_LQM_INT_EN BIT(7) /* Link Quality Monitor */
3334e45ad9SAndrew F. Davis
34cf13be5aSAndrew F. Davis #define DP83848_INT_EN_MASK \
35cf13be5aSAndrew F. Davis (DP83848_MISR_ANC_INT_EN | \
36cf13be5aSAndrew F. Davis DP83848_MISR_DUP_INT_EN | \
37cf13be5aSAndrew F. Davis DP83848_MISR_SPD_INT_EN | \
38cf13be5aSAndrew F. Davis DP83848_MISR_LINK_INT_EN)
39cf13be5aSAndrew F. Davis
401d1ae3c6SIoana Ciornei #define DP83848_MISR_RHF_INT BIT(8)
411d1ae3c6SIoana Ciornei #define DP83848_MISR_FHF_INT BIT(9)
421d1ae3c6SIoana Ciornei #define DP83848_MISR_ANC_INT BIT(10)
431d1ae3c6SIoana Ciornei #define DP83848_MISR_DUP_INT BIT(11)
441d1ae3c6SIoana Ciornei #define DP83848_MISR_SPD_INT BIT(12)
451d1ae3c6SIoana Ciornei #define DP83848_MISR_LINK_INT BIT(13)
461d1ae3c6SIoana Ciornei #define DP83848_MISR_ED_INT BIT(14)
471d1ae3c6SIoana Ciornei
481d1ae3c6SIoana Ciornei #define DP83848_INT_MASK \
491d1ae3c6SIoana Ciornei (DP83848_MISR_ANC_INT | \
501d1ae3c6SIoana Ciornei DP83848_MISR_DUP_INT | \
511d1ae3c6SIoana Ciornei DP83848_MISR_SPD_INT | \
521d1ae3c6SIoana Ciornei DP83848_MISR_LINK_INT)
531d1ae3c6SIoana Ciornei
dp83848_ack_interrupt(struct phy_device * phydev)5434e45ad9SAndrew F. Davis static int dp83848_ack_interrupt(struct phy_device *phydev)
5534e45ad9SAndrew F. Davis {
5634e45ad9SAndrew F. Davis int err = phy_read(phydev, DP83848_MISR);
5734e45ad9SAndrew F. Davis
5834e45ad9SAndrew F. Davis return err < 0 ? err : 0;
5934e45ad9SAndrew F. Davis }
6034e45ad9SAndrew F. Davis
dp83848_config_intr(struct phy_device * phydev)6134e45ad9SAndrew F. Davis static int dp83848_config_intr(struct phy_device *phydev)
6234e45ad9SAndrew F. Davis {
63cf13be5aSAndrew F. Davis int control, ret;
64cf13be5aSAndrew F. Davis
65cf13be5aSAndrew F. Davis control = phy_read(phydev, DP83848_MICR);
66cf13be5aSAndrew F. Davis if (control < 0)
67cf13be5aSAndrew F. Davis return control;
6834e45ad9SAndrew F. Davis
6934e45ad9SAndrew F. Davis if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
70aa2d603aSIoana Ciornei ret = dp83848_ack_interrupt(phydev);
71aa2d603aSIoana Ciornei if (ret)
72aa2d603aSIoana Ciornei return ret;
73aa2d603aSIoana Ciornei
74cf13be5aSAndrew F. Davis control |= DP83848_MICR_INT_OE;
75cf13be5aSAndrew F. Davis control |= DP83848_MICR_INTEN;
7634e45ad9SAndrew F. Davis
77cf13be5aSAndrew F. Davis ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK);
78cf13be5aSAndrew F. Davis if (ret < 0)
79cf13be5aSAndrew F. Davis return ret;
80aa2d603aSIoana Ciornei
81aa2d603aSIoana Ciornei ret = phy_write(phydev, DP83848_MICR, control);
82cf13be5aSAndrew F. Davis } else {
83cf13be5aSAndrew F. Davis control &= ~DP83848_MICR_INTEN;
84aa2d603aSIoana Ciornei ret = phy_write(phydev, DP83848_MICR, control);
85aa2d603aSIoana Ciornei if (ret)
86aa2d603aSIoana Ciornei return ret;
87aa2d603aSIoana Ciornei
88aa2d603aSIoana Ciornei ret = dp83848_ack_interrupt(phydev);
8934e45ad9SAndrew F. Davis }
9034e45ad9SAndrew F. Davis
91aa2d603aSIoana Ciornei return ret;
9234e45ad9SAndrew F. Davis }
9334e45ad9SAndrew F. Davis
dp83848_handle_interrupt(struct phy_device * phydev)941d1ae3c6SIoana Ciornei static irqreturn_t dp83848_handle_interrupt(struct phy_device *phydev)
951d1ae3c6SIoana Ciornei {
961d1ae3c6SIoana Ciornei int irq_status;
971d1ae3c6SIoana Ciornei
981d1ae3c6SIoana Ciornei irq_status = phy_read(phydev, DP83848_MISR);
991d1ae3c6SIoana Ciornei if (irq_status < 0) {
1001d1ae3c6SIoana Ciornei phy_error(phydev);
1011d1ae3c6SIoana Ciornei return IRQ_NONE;
1021d1ae3c6SIoana Ciornei }
1031d1ae3c6SIoana Ciornei
1041d1ae3c6SIoana Ciornei if (!(irq_status & DP83848_INT_MASK))
1051d1ae3c6SIoana Ciornei return IRQ_NONE;
1061d1ae3c6SIoana Ciornei
1071d1ae3c6SIoana Ciornei phy_trigger_machine(phydev);
1081d1ae3c6SIoana Ciornei
1091d1ae3c6SIoana Ciornei return IRQ_HANDLED;
1101d1ae3c6SIoana Ciornei }
1111d1ae3c6SIoana Ciornei
dp83848_config_init(struct phy_device * phydev)112b718e8c8SAlvaro Gamez Machado static int dp83848_config_init(struct phy_device *phydev)
113b718e8c8SAlvaro Gamez Machado {
114b718e8c8SAlvaro Gamez Machado int val;
115b718e8c8SAlvaro Gamez Machado
116b718e8c8SAlvaro Gamez Machado /* DP83620 always reports Auto Negotiation Ability on BMSR. Instead,
117b718e8c8SAlvaro Gamez Machado * we check initial value of BMCR Auto negotiation enable bit
118b718e8c8SAlvaro Gamez Machado */
119b718e8c8SAlvaro Gamez Machado val = phy_read(phydev, MII_BMCR);
120b718e8c8SAlvaro Gamez Machado if (!(val & BMCR_ANENABLE))
121b718e8c8SAlvaro Gamez Machado phydev->autoneg = AUTONEG_DISABLE;
122b718e8c8SAlvaro Gamez Machado
123b718e8c8SAlvaro Gamez Machado return 0;
124b718e8c8SAlvaro Gamez Machado }
125b718e8c8SAlvaro Gamez Machado
12634e45ad9SAndrew F. Davis static struct mdio_device_id __maybe_unused dp83848_tbl[] = {
12768336293SAndrew F. Davis { TI_DP83848C_PHY_ID, 0xfffffff0 },
12868336293SAndrew F. Davis { NS_DP83848C_PHY_ID, 0xfffffff0 },
12993b43fd1SAlvaro G. M { TI_DP83620_PHY_ID, 0xfffffff0 },
130d1782f7bSAndrew F. Davis { TLK10X_PHY_ID, 0xfffffff0 },
13134e45ad9SAndrew F. Davis { }
13234e45ad9SAndrew F. Davis };
13334e45ad9SAndrew F. Davis MODULE_DEVICE_TABLE(mdio, dp83848_tbl);
13434e45ad9SAndrew F. Davis
135b718e8c8SAlvaro Gamez Machado #define DP83848_PHY_DRIVER(_id, _name, _config_init) \
1362f67864bSAndrew F. Davis { \
1372f67864bSAndrew F. Davis .phy_id = _id, \
1382f67864bSAndrew F. Davis .phy_id_mask = 0xfffffff0, \
1392f67864bSAndrew F. Davis .name = _name, \
140dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ \
1412f67864bSAndrew F. Davis \
1422f67864bSAndrew F. Davis .soft_reset = genphy_soft_reset, \
143b718e8c8SAlvaro Gamez Machado .config_init = _config_init, \
1442f67864bSAndrew F. Davis .suspend = genphy_suspend, \
1452f67864bSAndrew F. Davis .resume = genphy_resume, \
1462f67864bSAndrew F. Davis \
1472f67864bSAndrew F. Davis /* IRQ related */ \
1482f67864bSAndrew F. Davis .config_intr = dp83848_config_intr, \
1491d1ae3c6SIoana Ciornei .handle_interrupt = dp83848_handle_interrupt, \
150*421cf80eSDiogo Silva \
151*421cf80eSDiogo Silva .flags = PHY_RST_AFTER_CLK_EN, \
1522f67864bSAndrew F. Davis }
1532f67864bSAndrew F. Davis
15434e45ad9SAndrew F. Davis static struct phy_driver dp83848_driver[] = {
155b718e8c8SAlvaro Gamez Machado DP83848_PHY_DRIVER(TI_DP83848C_PHY_ID, "TI DP83848C 10/100 Mbps PHY",
156c227ce44SHeiner Kallweit NULL),
157b718e8c8SAlvaro Gamez Machado DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY",
158c227ce44SHeiner Kallweit NULL),
159b718e8c8SAlvaro Gamez Machado DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY",
160b718e8c8SAlvaro Gamez Machado dp83848_config_init),
161b718e8c8SAlvaro Gamez Machado DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY",
162c227ce44SHeiner Kallweit NULL),
16334e45ad9SAndrew F. Davis };
16434e45ad9SAndrew F. Davis module_phy_driver(dp83848_driver);
16534e45ad9SAndrew F. Davis
16634e45ad9SAndrew F. Davis MODULE_DESCRIPTION("Texas Instruments DP83848 PHY driver");
1673d17cc39SAndrew F. Davis MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
1685f857575SAndrew Lunn MODULE_LICENSE("GPL v2");
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