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Searched refs:pci_set_byte (Results 1 – 23 of 23) sorted by relevance

/openbmc/qemu/hw/usb/
H A Dhcd-ehci-pci.c39 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); in usb_ehci_pci_realize()
42 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); in usb_ehci_pci_realize()
45 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ in usb_ehci_pci_realize()
46 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); in usb_ehci_pci_realize()
47 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); in usb_ehci_pci_realize()
51 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */ in usb_ehci_pci_realize()
52 pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ in usb_ehci_pci_realize()
/openbmc/qemu/hw/pci/
H A Dshpc.c221 pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); in shpc_reset()
224 pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0)); in shpc_reset()
234 pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0); in shpc_reset()
237 pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), in shpc_reset()
511 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); in shpc_cap_add_config()
512 pci_set_byte(config + SHPC_CAP_CxP, 0); in shpc_cap_add_config()
516 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); in shpc_cap_add_config()
677 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); in shpc_init()
678 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
679 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); in shpc_init()
[all …]
/openbmc/qemu/include/hw/pci/
H A Dpci.h445 pci_set_byte(uint8_t *config, uint8_t val) in pci_set_byte() function
514 pci_set_byte(&pci_config[PCI_REVISION_ID], val); in pci_config_set_revision()
526 pci_set_byte(&pci_config[PCI_CLASS_PROG], val); in pci_config_set_prog_interface()
532 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); in pci_config_set_interrupt_pin()
545 pci_set_byte(config, val & ~mask); in pci_byte_test_and_clear_mask()
553 pci_set_byte(config, val | mask); in pci_byte_test_and_set_mask()
614 pci_set_byte(config, (~mask & val) | (mask & rval)); in pci_set_byte_by_mask()
/openbmc/qemu/hw/vfio/
H A Dpci-quirks.c1605 pci_set_byte(pdev->config + pos++, 8); in vfio_add_nv_gpudirect_cap()
1606 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1607 pci_set_byte(pdev->config + pos++, '2'); in vfio_add_nv_gpudirect_cap()
1608 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1609 pci_set_byte(pdev->config + pos++, vdev->nv_gpudirect_clique << 3); in vfio_add_nv_gpudirect_cap()
1610 pci_set_byte(pdev->config + pos, 0); in vfio_add_nv_gpudirect_cap()
1663 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_LEN); in vfio_add_vmd_shadow_cap()
1664 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_VER); in vfio_add_vmd_shadow_cap()
H A Digd.c423 pci_set_byte(vdev->pdev.config + offset, data); in vfio_igd_quirk_bdsm_write()
H A Dpci.c2204 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); in vfio_add_std_cap()
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c595 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, in ich9_lpc_reset()
599 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, in ich9_lpc_reset()
602 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); in ich9_lpc_reset()
730 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, in ich9_lpc_realize()
/openbmc/qemu/hw/i386/xen/
H A Dxen_pvdevice.c103 pci_set_byte(pci_conf + PCI_REVISION_ID, d->revision); in xen_pv_realize()
/openbmc/qemu/hw/display/
H A Dvga-pci.c262 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); in pci_std_vga_realize()
293 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2); in pci_secondary_vga_realize()
H A Dbochs-display.c294 pci_set_byte(&s->pci.config[PCI_REVISION_ID], 2); in bochs_display_realize()
H A Dqxl.c2127 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2128 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
/openbmc/qemu/hw/i2c/
H A Dsmbus_ich9.c102 pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); in ich9_smbus_realize()
/openbmc/qemu/hw/pci-host/
H A Dbonito.c730 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); in bonito_pci_realize()
733 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); in bonito_pci_realize()
734 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); in bonito_pci_realize()
H A Dversatile.c471 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); in versatile_pci_host_realize()
H A Dgt64120.c1244 pci_set_byte(d->config + 0x3d, 0x01); in gt64120_pci_reset_hold()
/openbmc/qemu/hw/riscv/
H A Driscv-iommu-pci.c90 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); in riscv_iommu_pci_realize()
/openbmc/qemu/hw/ipack/
H A Dtpci200.c588 pci_set_byte(c + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */ in tpci200_realize()
590 pci_set_byte(c + PCI_CAPABILITY_LIST, 0x40); in tpci200_realize()
/openbmc/qemu/hw/net/
H A Deepro100.c491 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ in e100_pci_reset()
495 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ in e100_pci_reset()
497 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); in e100_pci_reset()
499 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18); in e100_pci_reset()
566 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000); in e100_pci_reset()
/openbmc/qemu/hw/ide/
H A Dvia.c140 pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe); in via_ide_reset()
H A Dsii3112.c259 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); in sii3112_pci_realize()
/openbmc/qemu/hw/audio/
H A Dvia-ac97.c444 pci_set_byte(pci_dev->config + 0x40, 1); /* codec ready */ in via_ac97_realize()
/openbmc/qemu/hw/virtio/
H A Dvirtio-pci.c704 pci_set_byte(buf, val); in virtio_address_space_read()
2078 pci_set_byte(&cfg_mask->cap.bar, ~0x0); in virtio_pci_device_plugged()
/openbmc/qemu/hw/xen/
H A Dxen_pt_config_init.c1998 case 1: pci_set_byte(s->dev.config + offset, (uint8_t)val); in xen_pt_config_reg_init()