/openbmc/qemu/target/ppc/translate/ |
H A D | fixedpoint-impl.c.inc | 38 tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); 40 tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop); 43 tcg_gen_mov_tl(cpu_gpr[ra], ea); 67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop); 98 lo = cpu_gpr[a->rt]; 99 hi = cpu_gpr[a->rt + 1]; 101 lo = cpu_gpr[a->rt + 1]; 102 hi = cpu_gpr[a->rt]; 236 gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); 242 gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf); [all …]
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H A D | spe-impl.c.inc | 21 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], 28 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 34 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); 39 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); 65 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 66 cpu_gpr[rB(ctx->opcode)]); \ 91 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 93 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 115 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 117 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ [all …]
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H A D | storage-ctrl-impl.c.inc | 33 gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]); 47 gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]); 75 gen_helper_SLBIAG(tcg_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); 89 gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); 103 gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); 117 gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); 140 gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env, 141 cpu_gpr[a->rb]); 145 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1); 149 tcg_gen_movi_tl(cpu_gpr[a->rt], 0); [all …]
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H A D | processor-ctrl-impl.c.inc | 38 gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]); 40 gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]); 62 gen_helper_book3s_msgsnd(tcg_env, cpu_gpr[a->rb]); 64 gen_helper_msgsnd(cpu_gpr[a->rb]); 78 gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); 91 gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
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H A D | vsx-impl.c.inc | 45 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 69 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 89 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 124 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 140 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 194 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 216 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 237 helper(tcg_env, EA, xt, cpu_gpr[a->rb]); 298 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 320 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); [all …]
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H A D | branch-impl.c.inc | 21 gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]);
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H A D | bhrb-impl.c.inc | 19 gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe);
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H A D | vmx-impl.c.inc | 45 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 68 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 91 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 338 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \ 418 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 455 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); 1433 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ 1721 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi); 1739 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F); 1794 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]); [all …]
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H A D | fp-impl.c.inc | 1002 tcg_gen_mov_tl(cpu_gpr[ra], ea); 1027 return do_lsfpsd(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, single);
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/openbmc/qemu/target/mips/tcg/ |
H A D | loong_translate.c | 53 tcg_gen_movi_tl(cpu_gpr[rd], 0); in gen_lext_DIV_G() 59 tcg_gen_mov_tl(cpu_gpr[rd], t0); in gen_lext_DIV_G() 63 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIV_G() 65 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lext_DIV_G() 106 tcg_gen_movi_tl(cpu_gpr[rd], 0); in gen_lext_DIVU_G() 110 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIVU_G() 112 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lext_DIVU_G() 157 tcg_gen_movi_tl(cpu_gpr[rd], 0); in gen_lext_MOD_G() 160 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); in gen_lext_MOD_G() 162 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lext_MOD_G() [all …]
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H A D | tx79_translate.c | 133 gen_logic_i64(cpu_gpr[a->rd], ax, bx); in trans_parallel_arith() 259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare() 434 tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); in trans_PPACW() 465 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 466 cpu_gpr[a->rd], bx, 2 * wlen * i, wlen); in trans_PEXTLx() 467 tcg_gen_deposit_i64(cpu_gpr[a->rd], in trans_PEXTLx() 468 cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen); in trans_PEXTLx() 511 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTLW() 530 gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); in trans_PEXTUW() 564 tcg_gen_movi_i64(cpu_gpr[a->rd], 0); in trans_PCPYH() [all …]
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H A D | translate.c | 1168 TCGv cpu_gpr[32], cpu_PC; variable 1193 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); in gen_load_gpr() 1197 tcg_gen_mov_tl(t, cpu_gpr[reg]); in gen_load_gpr() 1203 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); in gen_store_gpr() 1205 tcg_gen_mov_tl(cpu_gpr[reg], t); in gen_store_gpr() 1955 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); in gen_base_offset_addr() 2352 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); in gen_arith_imm() 2353 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); in gen_arith_imm() 2355 tcg_gen_movi_tl(cpu_gpr[rt], uimm); in gen_arith_imm() 2381 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); in gen_arith_imm() [all …]
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H A D | translate_addr_const.c | 30 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_lsa() 31 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lsa() 51 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_dlsa()
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H A D | octeon_translate.c | 59 tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); in trans_BADDU() 77 tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); in trans_DMUL() 148 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0); in trans_SEQNE() 150 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); in trans_SEQNE() 171 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm); in trans_SEQNEI() 173 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); in trans_SEQNEI()
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H A D | mips16e_translate.c.inc | 286 gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize); 309 gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize); 389 gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize); 588 tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm); 591 tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm); 1013 tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); 1016 tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]); 1019 tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]); 1022 tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]); 1028 tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); [all …]
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H A D | nanomips_translate.c.inc | 1046 tcg_gen_movi_tl(cpu_gpr[reg1], 1); 1053 tcg_gen_movi_tl(cpu_gpr[reg1], 0); 1061 gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u); 1171 tcg_gen_movi_tl(cpu_gpr[31], 1176 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); 1185 tcg_gen_movi_tl(cpu_gpr[rt], 1205 tcg_gen_movi_tl(cpu_gpr[31], 1405 gen_mfc0(ctx, cpu_gpr[rt], rs, extract32(ctx->opcode, 11, 3)); 1797 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * rd); 1800 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); [all …]
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H A D | translate.h | 185 extern TCGv cpu_gpr[32], cpu_PC;
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H A D | micromips_translate.c.inc | 864 gen_load_gpr(cpu_gpr[rd], rs_rt_enc[enc_rs]); 865 gen_load_gpr(cpu_gpr[re], rs_rt_enc[enc_rt]); 1059 gen_mfc0(ctx, cpu_gpr[rt], rs, (ctx->opcode >> 11) & 0x7); 3216 tcg_gen_movi_tl(cpu_gpr[reg], imm);
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/openbmc/qemu/target/ppc/ |
H A D | translate.c | 63 static TCGv cpu_gpr[32]; variable 102 cpu_gpr[i] = tcg_global_mem_new(tcg_env, in ppc_translate_init() 431 gen_load_spr(cpu_gpr[gprn], sprn); in spr_read_generic() 445 gen_store_spr(sprn, cpu_gpr[gprn]); in spr_write_generic() 453 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); in spr_write_generic32() 473 cpu_gpr[gprn]); in spr_core_write_generic() 491 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); in spr_core_write_generic32() 510 tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ in spr_write_CTRL_ST() 529 cpu_gpr[gprn]); in spr_write_CTRL() 547 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); in spr_write_clear() [all …]
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H A D | power8-pmu-regs.c.inc | 73 tcg_gen_andi_tl(t0, cpu_gpr[gprn], spr_mask); 98 tcg_gen_mov_tl(cpu_gpr[gprn], t0); 158 tcg_gen_mov_tl(cpu_gpr[gprn], t0); 180 gen_helper_store_mmcrA(tcg_env, cpu_gpr[gprn]); 188 gen_helper_read_pmc(cpu_gpr[gprn], tcg_env, t_sprn); 221 gen_helper_store_pmc(tcg_env, t_sprn, cpu_gpr[gprn]); 251 write_MMCR0_common(ctx, cpu_gpr[gprn]); 257 gen_helper_store_mmcr1(tcg_env, cpu_gpr[gprn]);
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/openbmc/qemu/target/loongarch/tcg/ |
H A D | translate.c | 24 TCGv cpu_gpr[32], cpu_pc; variable 181 return cpu_gpr[reg_num]; in gpr_src() 184 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src() 188 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src() 199 return cpu_gpr[reg_num]; in gpr_dst() 207 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 210 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 213 tcg_gen_ext32u_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 349 cpu_gpr[0] = NULL; in loongarch_translate_init() 351 cpu_gpr[i] = tcg_global_mem_new(tcg_env, in loongarch_translate_init()
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/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_rvzacas.c.inc | 42 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 52 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 54 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 55 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 59 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 60 tcg_gen_sari_tl(cpu_gprh[reg_num + 1], cpu_gpr[reg_num + 1], 63);
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/openbmc/qemu/target/riscv/ |
H A D | translate.c | 40 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; variable 345 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in get_gpr() 349 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in get_gpr() 361 return cpu_gpr[reg_num]; in get_gpr() 378 return cpu_gpr[reg_num]; in dest_gpr() 394 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 398 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 405 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); in gen_set_gpr() 415 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); in gen_set_gpri() 419 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); in gen_set_gpri() [all …]
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/openbmc/qemu/target/loongarch/ |
H A D | translate.h | 56 extern TCGv cpu_gpr[32], cpu_pc;
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/openbmc/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_branch.c.inc | 15 tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4));
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