1*a2b0a27dSPhilippe Mathieu-Daudé /*
2*a2b0a27dSPhilippe Mathieu-Daudé * Address Computation and Large Constant Instructions
3*a2b0a27dSPhilippe Mathieu-Daudé *
4*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2004-2005 Jocelyn Mayer
5*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2006 Marius Groeger (FPU operations)
6*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2020 Philippe Mathieu-Daudé
10*a2b0a27dSPhilippe Mathieu-Daudé *
11*a2b0a27dSPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.1-or-later
12*a2b0a27dSPhilippe Mathieu-Daudé */
13*a2b0a27dSPhilippe Mathieu-Daudé #include "qemu/osdep.h"
14*a2b0a27dSPhilippe Mathieu-Daudé #include "translate.h"
15*a2b0a27dSPhilippe Mathieu-Daudé
gen_lsa(DisasContext * ctx,int rd,int rt,int rs,int sa)16*a2b0a27dSPhilippe Mathieu-Daudé bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
17*a2b0a27dSPhilippe Mathieu-Daudé {
18*a2b0a27dSPhilippe Mathieu-Daudé TCGv t0;
19*a2b0a27dSPhilippe Mathieu-Daudé TCGv t1;
20*a2b0a27dSPhilippe Mathieu-Daudé
21*a2b0a27dSPhilippe Mathieu-Daudé if (rd == 0) {
22*a2b0a27dSPhilippe Mathieu-Daudé /* Treat as NOP. */
23*a2b0a27dSPhilippe Mathieu-Daudé return true;
24*a2b0a27dSPhilippe Mathieu-Daudé }
25*a2b0a27dSPhilippe Mathieu-Daudé t0 = tcg_temp_new();
26*a2b0a27dSPhilippe Mathieu-Daudé t1 = tcg_temp_new();
27*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(t0, rs);
28*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(t1, rt);
29*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_shli_tl(t0, t0, sa + 1);
30*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
31*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
32*a2b0a27dSPhilippe Mathieu-Daudé return true;
33*a2b0a27dSPhilippe Mathieu-Daudé }
34*a2b0a27dSPhilippe Mathieu-Daudé
gen_dlsa(DisasContext * ctx,int rd,int rt,int rs,int sa)35*a2b0a27dSPhilippe Mathieu-Daudé bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
36*a2b0a27dSPhilippe Mathieu-Daudé {
37*a2b0a27dSPhilippe Mathieu-Daudé TCGv t0;
38*a2b0a27dSPhilippe Mathieu-Daudé TCGv t1;
39*a2b0a27dSPhilippe Mathieu-Daudé
40*a2b0a27dSPhilippe Mathieu-Daudé check_mips_64(ctx);
41*a2b0a27dSPhilippe Mathieu-Daudé
42*a2b0a27dSPhilippe Mathieu-Daudé if (rd == 0) {
43*a2b0a27dSPhilippe Mathieu-Daudé /* Treat as NOP. */
44*a2b0a27dSPhilippe Mathieu-Daudé return true;
45*a2b0a27dSPhilippe Mathieu-Daudé }
46*a2b0a27dSPhilippe Mathieu-Daudé t0 = tcg_temp_new();
47*a2b0a27dSPhilippe Mathieu-Daudé t1 = tcg_temp_new();
48*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(t0, rs);
49*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(t1, rt);
50*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_shli_tl(t0, t0, sa + 1);
51*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
52*a2b0a27dSPhilippe Mathieu-Daudé return true;
53*a2b0a27dSPhilippe Mathieu-Daudé }
54