Home
last modified time | relevance | path

Searched refs:clk_set_parent (Results 1 – 25 of 107) sorted by relevance

12345

/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sx.c177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
498 clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); in imx6sx_clocks_init()
502 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); in imx6sx_clocks_init()
503 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); in imx6sx_clocks_init()
[all …]
H A Dclk-imx6q.c275 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
499 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
501 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
502 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
503 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
504 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
505 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
930 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); in imx6q_clocks_init()
932 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
[all …]
H A Dclk-imx6ul.c180 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
182 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
183 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
184 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
185 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
186 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
514 clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
515 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk); in imx6ul_clocks_init()
516 clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk); in imx6ul_clocks_init()
[all …]
H A Dclk-vf610.c236 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init()
237 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init()
238 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init()
239 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init()
240 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init()
241 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init()
242 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init()
447 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
452 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); in vf610_clocks_init()
457 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); in vf610_clocks_init()
[all …]
H A Dclk-imx6sl.c234 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
235 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
236 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
237 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
238 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
239 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
240 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
434 clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); in imx6sl_clocks_init()
437 clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, in imx6sl_clocks_init()
440 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, in imx6sl_clocks_init()
H A Dclk-cpu.c48 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate()
55 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
59 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
H A Dclk-imx5.c277 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init()
347 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
348 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
438 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
441 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
442 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
592 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
593 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx53_clocks_init()
600 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
603 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
H A Dclk-imx7d.c869 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
870 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
874 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
876 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
879 clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); in imx7d_clocks_init()
/openbmc/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-clk.c134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dtegra124-cpufreq.c37 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
43 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
48 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
141 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpufreq_suspend()
167 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpufreq_resume()
H A Dimx6q-cpufreq.c128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
130 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
133 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
136 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
139 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
142 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
143 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
146 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
H A Dimx-cpufreq-dt.c66 clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
67 clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk); in imx7ulp_target_intermediate()
70 clk_set_parent(imx7ulp_clks[ARM].clk, in imx7ulp_target_intermediate()
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
H A Dkirkwood-cpufreq.c65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
68 clk_set_parent(priv.powersave_clk, priv.ddr_clk); in kirkwood_cpufreq_target()
H A Dmediatek-cpufreq.c265 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
278 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
284 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
301 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
303 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-clk.c79 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8186_set_audio_int_bus_parent()
103 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
119 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
128 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
138 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
164 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
180 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
199 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
265 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8186_afe_enable_clock()
[all …]
/openbmc/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
229 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8192_afe_enable_clock()
[all …]
/openbmc/linux/sound/soc/samsung/
H A Dsmdk_spdif.c55 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy()
56 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy()
57 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
/openbmc/linux/sound/soc/sof/mediatek/mt8195/
H A Dmt8195-clk.c120 ret = clk_set_parent(priv->clk[CLK_TOP_ADSP], in adsp_default_clk_init()
127 ret = clk_set_parent(priv->clk[CLK_TOP_AUDIO_LOCAL_BUS], in adsp_default_clk_init()
134 ret = clk_set_parent(priv->clk[CLK_TOP_AUDIO_H], in adsp_default_clk_init()
/openbmc/linux/arch/m68k/coldfire/
H A Dclk.c130 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
135 EXPORT_SYMBOL(clk_set_parent);
/openbmc/linux/drivers/clk/ti/
H A Dclk-33xx.c294 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
297 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
307 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
/openbmc/linux/arch/mips/lantiq/
H A Dclk.c168 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
172 EXPORT_SYMBOL(clk_set_parent);
/openbmc/linux/drivers/devfreq/
H A Dimx8m-ddrc.c193 ret = clk_set_parent(priv->dram_core, new_dram_core_parent); in imx8m_ddrc_set_freq()
197 ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent); in imx8m_ddrc_set_freq()
203 ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent); in imx8m_ddrc_set_freq()
H A Dmtk-cci-devfreq.c173 ret = clk_set_parent(drv->cci_clk, drv->inter_clk); in mtk_ccifreq_target()
183 clk_set_parent(drv->cci_clk, cci_pll); in mtk_ccifreq_target()
188 ret = clk_set_parent(drv->cci_clk, cci_pll); in mtk_ccifreq_target()
/openbmc/u-boot/arch/arm/include/asm/kona-common/
H A Dclk.h23 int clk_set_parent(struct clk *clk, struct clk *parent);
/openbmc/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c187 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
209 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
210 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
215 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
354 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()

12345