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Searched refs:cfg_base (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/drivers/net/can/sja1000/
H A Dpeak_pci.c37 void __iomem *cfg_base; /* Common for all channels */ member
162 void __iomem *cfg_base; /* Common for all channels */ member
180 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL; in pita_set_scl_highz()
182 writeb(gp_outen, card->cfg_base + PITA_GPOEN); in pita_set_scl_highz()
187 u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA; in pita_set_sda_highz()
189 writeb(gp_outen, card->cfg_base + PITA_GPOEN); in pita_set_sda_highz()
205 gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA; in pita_setsda()
206 writeb(gp_out, card->cfg_base + PITA_GPOUT); in pita_setsda()
209 gp_outen = readb(card->cfg_base + PITA_GPOEN); in pita_setsda()
215 writeb(gp_outen, card->cfg_base + PITA_GPOEN); in pita_setsda()
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/openbmc/linux/arch/mips/pci/
H A Dops-lantiq.c29 unsigned long cfg_base; in ltq_pci_config_access() local
41 cfg_base = (unsigned long) ltq_pci_mapped_cfg; in ltq_pci_config_access()
42 cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << in ltq_pci_config_access()
47 ltq_w32(swab32(*data), ((u32 *)cfg_base)); in ltq_pci_config_access()
49 *data = ltq_r32(((u32 *)(cfg_base))); in ltq_pci_config_access()
55 cfg_base = (unsigned long) ltq_pci_mapped_cfg; in ltq_pci_config_access()
56 cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; in ltq_pci_config_access()
57 temp = ltq_r32(((u32 *)(cfg_base))); in ltq_pci_config_access()
59 cfg_base = (unsigned long) ltq_pci_mapped_cfg; in ltq_pci_config_access()
60 cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; in ltq_pci_config_access()
[all …]
H A Dpci-ar71xx.c49 void __iomem *cfg_base; member
109 void __iomem *base = apc->cfg_base; in ar71xx_pci_check_error()
147 void __iomem *base = apc->cfg_base; in ar71xx_pci_local_write()
164 void __iomem *base = apc->cfg_base; in ar71xx_pci_set_cfgaddr()
180 void __iomem *base = apc->cfg_base; in ar71xx_pci_read_config()
204 void __iomem *base = apc->cfg_base; in ar71xx_pci_write_config()
339 apc->cfg_base = devm_platform_ioremap_resource_byname(pdev, in ar71xx_pci_probe()
341 if (IS_ERR(apc->cfg_base)) in ar71xx_pci_probe()
342 return PTR_ERR(apc->cfg_base); in ar71xx_pci_probe()
H A Dpci-alchemy.c105 unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; in config_access() local
130 cfg_base = (1 << device) << 11; in config_access()
132 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); in config_access()
137 offset |= cfg_base & ~PAGE_MASK; in config_access()
140 cfg_base = cfg_base & PAGE_MASK; in config_access()
145 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; in config_access()
146 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; in config_access()
/openbmc/u-boot/drivers/pci/
H A Dpci-rcar-gen2.c87 fdt_addr_t cfg_base; member
114 return priv->cfg_base + (PCI_DEV(bdf) >> 1) * 0x100 + (offset & ~3); in get_bus_address()
124 writel(reg, priv->cfg_base + RCAR_AHBPCI_WIN1_CTR_REG); in setup_bus_address()
185 clrsetbits_le32(priv->cfg_base + RCAR_USBCTR_REG, in rcar_gen2_pci_probe()
189 clrbits_le32(priv->cfg_base + RCAR_USBCTR_REG, RCAR_USBCTR_PLL_RST); in rcar_gen2_pci_probe()
192 writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); in rcar_gen2_pci_probe()
194 priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); in rcar_gen2_pci_probe()
196 priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); in rcar_gen2_pci_probe()
198 priv->cfg_base + RCAR_AHBPCI_WIN2_CTR_REG); in rcar_gen2_pci_probe()
199 setbits_le32(priv->cfg_base + RCAR_PCI_ARBITER_CTR_REG, in rcar_gen2_pci_probe()
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H A Dpcie_xilinx.c19 void *cfg_base; member
36 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); in pcie_xilinx_link_up()
76 addr = pcie->cfg_base; in pcie_xilinx_config_address()
154 pcie->cfg_base = map_physmem(reg_res.start, in pcie_xilinx_ofdata_to_platdata()
H A Dpcie_ecam_generic.c21 void *cfg_base; member
44 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
118 pcie->cfg_base = map_physmem(reg_res.start, in pci_generic_ecam_ofdata_to_platdata()
H A Dpcie_dw_mvebu.c110 void *cfg_base; member
198 atu_type, (u64)pcie->cfg_base, in set_cfg_address()
200 va_address = (uintptr_t)pcie->cfg_base; in set_cfg_address()
556 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, in pcie_dw_mvebu_ofdata_to_platdata()
558 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) in pcie_dw_mvebu_ofdata_to_platdata()
/openbmc/linux/sound/soc/intel/avs/
H A Dpath.c245 cfg->base.cpc = t->cfg_base->cpc; in avs_copier_create()
246 cfg->base.ibs = t->cfg_base->ibs; in avs_copier_create()
247 cfg->base.obs = t->cfg_base->obs; in avs_copier_create()
248 cfg->base.is_pages = t->cfg_base->is_pages; in avs_copier_create()
310 cfg->base.cpc = t->cfg_base->cpc; in avs_peakvol_create()
311 cfg->base.ibs = t->cfg_base->ibs; in avs_peakvol_create()
312 cfg->base.obs = t->cfg_base->obs; in avs_peakvol_create()
313 cfg->base.is_pages = t->cfg_base->is_pages; in avs_peakvol_create()
333 cfg.base.cpc = t->cfg_base->cpc; in avs_updown_mix_create()
334 cfg.base.ibs = t->cfg_base->ibs; in avs_updown_mix_create()
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H A Dtopology.h180 struct avs_tplg_modcfg_base *cfg_base; member
H A Dtopology.c1047 .offset = offsetof(struct avs_tplg_module, cfg_base),
/openbmc/linux/drivers/perf/
H A Dalibaba_uncore_drw_pmu.c94 void __iomem *cfg_base; member
294 cycle_high = readl(drw_pmu->cfg_base + ALI_DRW_PMU_CYCLE_CNT_HIGH); in ali_drw_pmu_read_counter()
296 cycle_low = readl(drw_pmu->cfg_base + ALI_DRW_PMU_CYCLE_CNT_LOW); in ali_drw_pmu_read_counter()
301 return readl(drw_pmu->cfg_base + in ali_drw_pmu_read_counter()
331 drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL); in ali_drw_pmu_event_set_period()
335 writel(pre_val, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_PRELOAD); in ali_drw_pmu_event_set_period()
339 writel(0x0, drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL); in ali_drw_pmu_event_set_period()
349 val = readl(drw_pmu->cfg_base + reg); in ali_drw_pmu_enable_counter()
357 writel(val, drw_pmu->cfg_base + reg); in ali_drw_pmu_enable_counter()
367 val = readl(drw_pmu->cfg_base + reg); in ali_drw_pmu_disable_counter()
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/openbmc/linux/drivers/pci/controller/
H A Dpci-xgene.c66 void __iomem *cfg_base; member
107 return port->cfg_base + AXI_EP_CFG_ACCESS; in xgene_pcie_get_cfg_base()
109 return port->cfg_base; in xgene_pcie_get_cfg_base()
245 port->cfg_base = cfg->win; in xgene_pcie_ecam_init()
355 port->cfg_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
356 if (IS_ERR(port->cfg_base)) in xgene_pcie_map_reg()
357 return PTR_ERR(port->cfg_base); in xgene_pcie_map_reg()
482 void __iomem *cfg_base = port->cfg_base; in xgene_pcie_setup_ib_reg() local
507 bar_addr = cfg_base + PCI_BASE_ADDRESS_0; in xgene_pcie_setup_ib_reg()
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpci-meson.c69 void __iomem *cfg_base; member
117 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); in meson_pcie_get_mems()
118 if (IS_ERR(mp->cfg_base)) in meson_pcie_get_mems()
119 return PTR_ERR(mp->cfg_base); in meson_pcie_get_mems()
224 return readl(mp->cfg_base + reg); in meson_cfg_readl()
229 writel(val, mp->cfg_base + reg); in meson_cfg_writel()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dcfg_space.c72 u8 *cfg_base = vgpu_cfg_space(vgpu); in vgpu_pci_cfg_mem_write() local
79 old = cfg_base[off + i]; in vgpu_pci_cfg_mem_write()
90 cfg_base[off + i] = (old & ~mask) | new; in vgpu_pci_cfg_mem_write()
95 memcpy(cfg_base + off + i, src + i, bytes - i); in vgpu_pci_cfg_mem_write()
/openbmc/qemu/hw/ppc/
H A Dppc440_uc.c744 uint64_t cfg_base; member
793 ret = s->cfg_base >> 32; in dcr_read_pcie()
796 ret = s->cfg_base; in dcr_read_pcie()
873 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); in dcr_write_pcie()
876 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; in dcr_write_pcie()
889 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); in dcr_write_pcie()
/openbmc/linux/drivers/soc/ti/
H A Dpruss.c348 reg = pruss->cfg_base + reg_offset; in pruss_clk_mux_setup()
442 pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res)); in pruss_cfg_of_init()
443 if (!pruss->cfg_base) { in pruss_cfg_of_init()
452 pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base, in pruss_cfg_of_init()
/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c73 return rc->cfg_base + (where & 0xfff); in cdns_pci_map_bus()
554 rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); in cdns_pcie_host_setup()
555 if (IS_ERR(rc->cfg_base)) in cdns_pcie_host_setup()
556 return PTR_ERR(rc->cfg_base); in cdns_pcie_host_setup()
H A Dpcie-cadence.h326 void __iomem *cfg_base; member
/openbmc/qemu/include/hw/pci-host/
H A Dxilinx-pcie.h49 uint64_t cfg_base, cfg_size; member
/openbmc/linux/include/linux/
H A Dpruss_driver.h97 void __iomem *cfg_base; member
/openbmc/qemu/hw/mips/
H A Dboston.c429 hwaddr cfg_base, uint64_t cfg_size, in xilinx_pcie_init() argument
439 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); in xilinx_pcie_init()
447 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); in xilinx_pcie_init()
/openbmc/qemu/hw/pci-host/
H A Dxilinx-pcie.c161 DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
/openbmc/linux/drivers/net/usb/
H A Dsmsc75xx.c1536 int cfg_base = WUF_CFGX + filter * 4; in smsc75xx_write_wuff() local
1540 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg); in smsc75xx_write_wuff()