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Searched refs:bcr (Results 1 – 25 of 63) sorted by relevance

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/openbmc/qemu/hw/ppc/
H A Dppc4xx_sdram.c128 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr, in sdram_bank_set_bcr() argument
134 bank->bcr = bcr; in sdram_bank_set_bcr()
137 if (enabled && (bcr & 1)) { in sdram_bank_set_bcr()
153 uint32_t bcr; in sdram_ddr_bcr() local
157 bcr = 0; in sdram_ddr_bcr()
160 bcr = 0x20000; in sdram_ddr_bcr()
163 bcr = 0x40000; in sdram_ddr_bcr()
166 bcr = 0x60000; in sdram_ddr_bcr()
169 bcr = 0x80000; in sdram_ddr_bcr()
172 bcr = 0xA0000; in sdram_ddr_bcr()
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H A Dppc4xx_devs.c359 ret = ebc->bcr[0]; in dcr_read_ebc()
362 ret = ebc->bcr[1]; in dcr_read_ebc()
365 ret = ebc->bcr[2]; in dcr_read_ebc()
368 ret = ebc->bcr[3]; in dcr_read_ebc()
371 ret = ebc->bcr[4]; in dcr_read_ebc()
374 ret = ebc->bcr[5]; in dcr_read_ebc()
377 ret = ebc->bcr[6]; in dcr_read_ebc()
380 ret = ebc->bcr[7]; in dcr_read_ebc()
497 ebc->bcr[0] = 0xFFE28000; in ppc405_ebc_reset()
500 ebc->bcr[i] = 0x00000000; in ppc405_ebc_reset()
/openbmc/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c141 u32 bcr[FMC2_MAX_EBI_CE]; member
183 u32 bcr; in stm32_fmc2_ebi_check_mux() local
186 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
190 if (bcr & FMC2_BCR_MTYP) in stm32_fmc2_ebi_check_mux()
200 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); in stm32_fmc2_ebi_check_waitcfg() local
203 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_waitcfg()
207 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) in stm32_fmc2_ebi_check_waitcfg()
217 u32 bcr; in stm32_fmc2_ebi_check_sync_trans() local
220 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_sync_trans()
224 if (bcr & FMC2_BCR_BURSTEN) in stm32_fmc2_ebi_check_sync_trans()
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/openbmc/linux/drivers/spi/
H A Dspi-intel-pci.c20 u32 bcr; in intel_spi_pci_set_writeable() local
23 pci_read_config_dword(pdev, BCR, &bcr); in intel_spi_pci_set_writeable()
24 if (!(bcr & BCR_WPD)) { in intel_spi_pci_set_writeable()
25 bcr |= BCR_WPD; in intel_spi_pci_set_writeable()
26 pci_write_config_dword(pdev, BCR, bcr); in intel_spi_pci_set_writeable()
27 pci_read_config_dword(pdev, BCR, &bcr); in intel_spi_pci_set_writeable()
30 return bcr & BCR_WPD; in intel_spi_pci_set_writeable()
/openbmc/qemu/hw/net/
H A Dpcnet.h27 #define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
28 #define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
29 #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
30 #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
31 #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
43 uint16_t bcr[32]; member
H A Dpcnet.c682 s->bcr[BCR_BSBC] &= ~0x0080; in pcnet_s_reset()
1515 s->bcr[rap] = val; in pcnet_bcr_writew()
1531 val = s->bcr[rap] & ~0x8000; in pcnet_bcr_readw()
1535 val = rap < 32 ? s->bcr[rap] : 0; in pcnet_bcr_readw()
1548 s->bcr[BCR_MSRDA] = 0x0005; in pcnet_h_reset()
1549 s->bcr[BCR_MSWRA] = 0x0005; in pcnet_h_reset()
1550 s->bcr[BCR_MC ] = 0x0002; in pcnet_h_reset()
1551 s->bcr[BCR_LNKST] = 0x00c0; in pcnet_h_reset()
1552 s->bcr[BCR_LED1 ] = 0x0084; in pcnet_h_reset()
1553 s->bcr[BCR_LED2 ] = 0x0088; in pcnet_h_reset()
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/openbmc/linux/arch/arc/include/asm/
H A Ddsp-impl.h131 struct bcr_generic bcr; in dsp_exist() local
133 READ_BCR(ARC_AUX_DSP_BUILD, bcr); in dsp_exist()
134 return !!bcr.ver; in dsp_exist()
139 struct bcr_generic bcr; in agu_exist() local
141 READ_BCR(ARC_AUX_AGU_BUILD, bcr); in agu_exist()
142 return !!bcr.ver; in agu_exist()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-synquacer.c260 unsigned char bsr, bcr; in synquacer_i2c_master_start() local
268 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_master_start()
269 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); in synquacer_i2c_master_start()
272 !(bcr & SYNQUACER_I2C_BCR_MSS)) { in synquacer_i2c_master_start()
279 writeb(bcr | SYNQUACER_I2C_BCR_SCC, in synquacer_i2c_master_start()
282 if (bcr & SYNQUACER_I2C_BCR_MSS) { in synquacer_i2c_master_start()
288 writeb(bcr | SYNQUACER_I2C_BCR_MSS | in synquacer_i2c_master_start()
297 bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_master_start()
298 dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr); in synquacer_i2c_master_start()
301 !(bcr & SYNQUACER_I2C_BCR_MSS)) { in synquacer_i2c_master_start()
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/openbmc/qemu/target/arm/
H A Dhyp_gdbstub.c60 .bcr = 0x1, /* BCR E=1, enable */ in insert_hw_breakpoint()
68 brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */ in insert_hw_breakpoint()
69 brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */ in insert_hw_breakpoint()
H A Ddebug_helper.c176 uint64_t bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches() local
194 bcr = env->cp15.dbgbcr[lbn]; in linked_bp_matches()
196 if (extract64(bcr, 0, 1) == 0) { in linked_bp_matches()
201 bt = extract64(bcr, 20, 4); in linked_bp_matches()
657 uint64_t bcr = env->cp15.dbgbcr[n]; in hw_breakpoint_update() local
667 if (!extract64(bcr, 0, 1)) { in hw_breakpoint_update()
672 bt = extract64(bcr, 20, 4); in hw_breakpoint_update()
707 int bas = extract64(bcr, 5, 4); in hw_breakpoint_update()
/openbmc/linux/drivers/net/can/cc770/
H A Dcc770_isa.c74 static u8 bcr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
99 module_param_array(bcr, byte, NULL, 0444);
100 MODULE_PARM_DESC(bcr, "Bus configuration register (default=0x40 [CBY])");
246 if (bcr[idx] != 0xff) in cc770_isa_probe()
247 priv->bus_config = bcr[idx]; in cc770_isa_probe()
248 else if (bcr[0] != 0xff) in cc770_isa_probe()
249 priv->bus_config = bcr[0]; in cc770_isa_probe()
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Ddct_v1.c21 u64 *pid, unsigned int *dcr, unsigned int *bcr) in i3c_hci_dct_get_val() argument
35 *bcr = FIELD_GET(W2_MASK(79, 72), dct_entry_data[2]); in i3c_hci_dct_get_val()
H A Ddct.h14 u64 *pid, unsigned int *dcr, unsigned int *bcr);
H A Dcmd_v2.c246 unsigned int dcr, bcr; in hci_cmd_v2_daa() local
294 bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]); in hci_cmd_v2_daa()
297 next_addr, pid, dcr, bcr); in hci_cmd_v2_daa()
/openbmc/qemu/include/hw/i3c/
H A Di3c.h139 uint8_t bcr; member
229 int i3c_do_entdaa(I3CBus *bus, uint8_t address, uint64_t *pid, uint8_t *bcr,
260 uint8_t bcr, uint64_t pid);
269 uint8_t addr, uint8_t dcr, uint8_t bcr,
/openbmc/u-boot/arch/arc/include/asm/
H A Darcregs.h31 #define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) argument
/openbmc/qemu/hw/i3c/
H A Dcore.c28 DEFINE_PROP_UINT8("bcr", struct I3CTarget, bcr, 0),
396 data[read_count] = t->bcr; in i3c_target_handle_ccc_read()
419 *data = t->bcr; in i3c_target_handle_ccc_read()
537 uint8_t bcr, uint64_t pid) in i3c_target_new() argument
544 qdev_prop_set_uint8(dev, "bcr", bcr); in i3c_target_new()
561 uint8_t dcr, uint8_t bcr, uint64_t pid) in i3c_target_create_simple() argument
563 I3CTarget *dev = i3c_target_new(name, addr, dcr, bcr, pid); in i3c_target_create_simple()
/openbmc/linux/include/linux/i3c/
H A Ddevice.h89 #define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6)) argument
123 u8 bcr; member
H A Dccc.h116 u8 bcr; member
188 u8 bcr; member
/openbmc/linux/include/soc/arc/
H A Dmcip.h91 #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum)) argument
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h42 uint bcr; /* DMA byte count register */ member
103 uint bcr; /* DMA byte count register */ member
/openbmc/qemu/include/hw/ppc/
H A Dppc4xx.h91 uint32_t bcr[8]; member
105 uint32_t bcr; member
/openbmc/linux/arch/arc/mm/
H A Dtlb.c572 unsigned int bcr, u_dtlb, u_itlb, sasid; in arc_mmu_mumbojumbo() local
578 bcr = read_aux_reg(ARC_REG_MMU_BCR); in arc_mmu_mumbojumbo()
579 mmu->ver = (bcr >> 24); in arc_mmu_mumbojumbo()
582 mmu3 = (struct bcr_mmu_3 *)&bcr; in arc_mmu_mumbojumbo()
590 mmu4 = (struct bcr_mmu_4 *)&bcr; in arc_mmu_mumbojumbo()
/openbmc/linux/arch/arc/kernel/
H A Dsetup.c293 struct bcr_generic bcr; in arc_cpu_mumbojumbo() local
338 READ_BCR(ARC_REG_SMART_BCR, bcr); in arc_cpu_mumbojumbo()
339 smart = bcr.ver ? 1 : 0; in arc_cpu_mumbojumbo()
341 READ_BCR(ARC_REG_RTT_BCR, bcr); in arc_cpu_mumbojumbo()
342 rtt = bcr.ver ? 1 : 0; in arc_cpu_mumbojumbo()
/openbmc/u-boot/drivers/spi/
H A Dich.h54 uint32_t bcr; member
191 int bcr; member

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