1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 21853030eSSimon Glass /* 31853030eSSimon Glass * Copyright (c) 2011 The Chromium OS Authors. 41853030eSSimon Glass * 51853030eSSimon Glass * This file is derived from the flashrom project. 61853030eSSimon Glass */ 71853030eSSimon Glass 89eb4339bSBin Meng #ifndef _ICH_H_ 99eb4339bSBin Meng #define _ICH_H_ 109eb4339bSBin Meng 111853030eSSimon Glass struct ich7_spi_regs { 121853030eSSimon Glass uint16_t spis; 131853030eSSimon Glass uint16_t spic; 141853030eSSimon Glass uint32_t spia; 151853030eSSimon Glass uint64_t spid[8]; 161853030eSSimon Glass uint64_t _pad; 171853030eSSimon Glass uint32_t bbar; 181853030eSSimon Glass uint16_t preop; 191853030eSSimon Glass uint16_t optype; 201853030eSSimon Glass uint8_t opmenu[8]; 211853030eSSimon Glass } __packed; 221853030eSSimon Glass 231853030eSSimon Glass struct ich9_spi_regs { 241853030eSSimon Glass uint32_t bfpr; /* 0x00 */ 251853030eSSimon Glass uint16_t hsfs; 261853030eSSimon Glass uint16_t hsfc; 271853030eSSimon Glass uint32_t faddr; 281853030eSSimon Glass uint32_t _reserved0; 291853030eSSimon Glass uint32_t fdata[16]; /* 0x10 */ 301853030eSSimon Glass uint32_t frap; /* 0x50 */ 311853030eSSimon Glass uint32_t freg[5]; 321853030eSSimon Glass uint32_t _reserved1[3]; 331853030eSSimon Glass uint32_t pr[5]; /* 0x74 */ 341853030eSSimon Glass uint32_t _reserved2[2]; 351853030eSSimon Glass uint8_t ssfs; /* 0x90 */ 361853030eSSimon Glass uint8_t ssfc[3]; 371853030eSSimon Glass uint16_t preop; /* 0x94 */ 381853030eSSimon Glass uint16_t optype; 391853030eSSimon Glass uint8_t opmenu[8]; /* 0x98 */ 401853030eSSimon Glass uint32_t bbar; 411853030eSSimon Glass uint8_t _reserved3[12]; 425093badbSSimon Glass uint32_t fdoc; /* 0xb0 */ 431853030eSSimon Glass uint32_t fdod; 441853030eSSimon Glass uint8_t _reserved4[8]; 455093badbSSimon Glass uint32_t afc; /* 0xc0 */ 461853030eSSimon Glass uint32_t lvscc; 471853030eSSimon Glass uint32_t uvscc; 481853030eSSimon Glass uint8_t _reserved5[4]; 495093badbSSimon Glass uint32_t fpb; /* 0xd0 */ 501853030eSSimon Glass uint8_t _reserved6[28]; 515093badbSSimon Glass uint32_t srdl; /* 0xf0 */ 521853030eSSimon Glass uint32_t srdc; 535093badbSSimon Glass uint32_t scs; 545093badbSSimon Glass uint32_t bcr; 551853030eSSimon Glass } __packed; 561853030eSSimon Glass 571853030eSSimon Glass enum { 581853030eSSimon Glass SPIS_SCIP = 0x0001, 591853030eSSimon Glass SPIS_GRANT = 0x0002, 601853030eSSimon Glass SPIS_CDS = 0x0004, 611853030eSSimon Glass SPIS_FCERR = 0x0008, 621853030eSSimon Glass SSFS_AEL = 0x0010, 631853030eSSimon Glass SPIS_LOCK = 0x8000, 641853030eSSimon Glass SPIS_RESERVED_MASK = 0x7ff0, 651853030eSSimon Glass SSFS_RESERVED_MASK = 0x7fe2 661853030eSSimon Glass }; 671853030eSSimon Glass 681853030eSSimon Glass enum { 691853030eSSimon Glass SPIC_SCGO = 0x000002, 701853030eSSimon Glass SPIC_ACS = 0x000004, 711853030eSSimon Glass SPIC_SPOP = 0x000008, 721853030eSSimon Glass SPIC_DBC = 0x003f00, 731853030eSSimon Glass SPIC_DS = 0x004000, 741853030eSSimon Glass SPIC_SME = 0x008000, 751853030eSSimon Glass SSFC_SCF_MASK = 0x070000, 761853030eSSimon Glass SSFC_RESERVED = 0xf80000, 771853030eSSimon Glass 781853030eSSimon Glass /* Mask for speed byte, biuts 23:16 of SSFC */ 791853030eSSimon Glass SSFC_SCF_33MHZ = 0x01, 801853030eSSimon Glass }; 811853030eSSimon Glass 821853030eSSimon Glass enum { 831853030eSSimon Glass HSFS_FDONE = 0x0001, 841853030eSSimon Glass HSFS_FCERR = 0x0002, 851853030eSSimon Glass HSFS_AEL = 0x0004, 861853030eSSimon Glass HSFS_BERASE_MASK = 0x0018, 871853030eSSimon Glass HSFS_BERASE_SHIFT = 3, 881853030eSSimon Glass HSFS_SCIP = 0x0020, 891853030eSSimon Glass HSFS_FDOPSS = 0x2000, 901853030eSSimon Glass HSFS_FDV = 0x4000, 911853030eSSimon Glass HSFS_FLOCKDN = 0x8000 921853030eSSimon Glass }; 931853030eSSimon Glass 941853030eSSimon Glass enum { 951853030eSSimon Glass HSFC_FGO = 0x0001, 961853030eSSimon Glass HSFC_FCYCLE_MASK = 0x0006, 971853030eSSimon Glass HSFC_FCYCLE_SHIFT = 1, 981853030eSSimon Glass HSFC_FDBC_MASK = 0x3f00, 991853030eSSimon Glass HSFC_FDBC_SHIFT = 8, 1001853030eSSimon Glass HSFC_FSMIE = 0x8000 1011853030eSSimon Glass }; 1021853030eSSimon Glass 1031853030eSSimon Glass enum { 1041853030eSSimon Glass ICH_MAX_CMD_LEN = 5, 1051853030eSSimon Glass }; 1061853030eSSimon Glass 1071853030eSSimon Glass struct spi_trans { 1081853030eSSimon Glass uint8_t cmd[ICH_MAX_CMD_LEN]; 1091853030eSSimon Glass int cmd_len; 1101853030eSSimon Glass const uint8_t *out; 1111853030eSSimon Glass uint32_t bytesout; 1121853030eSSimon Glass uint8_t *in; 1131853030eSSimon Glass uint32_t bytesin; 1141853030eSSimon Glass uint8_t type; 1151853030eSSimon Glass uint8_t opcode; 1161853030eSSimon Glass uint32_t offset; 1171853030eSSimon Glass }; 1181853030eSSimon Glass 1194759dffeSStefan Roese #define SPI_OPCODE_WRSR 0x01 1204759dffeSStefan Roese #define SPI_OPCODE_PAGE_PROGRAM 0x02 1214759dffeSStefan Roese #define SPI_OPCODE_READ 0x03 1224759dffeSStefan Roese #define SPI_OPCODE_WRDIS 0x04 1234759dffeSStefan Roese #define SPI_OPCODE_RDSR 0x05 1249eb4339bSBin Meng #define SPI_OPCODE_WREN 0x06 1259eb4339bSBin Meng #define SPI_OPCODE_FAST_READ 0x0b 1264759dffeSStefan Roese #define SPI_OPCODE_ERASE_SECT 0x20 1274759dffeSStefan Roese #define SPI_OPCODE_READ_ID 0x9f 1284759dffeSStefan Roese #define SPI_OPCODE_ERASE_BLOCK 0xd8 1294759dffeSStefan Roese 1304759dffeSStefan Roese #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 1314759dffeSStefan Roese #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 1324759dffeSStefan Roese #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 1334759dffeSStefan Roese #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 1344759dffeSStefan Roese 1354759dffeSStefan Roese #define SPI_OPMENU_0 SPI_OPCODE_WRSR 1364759dffeSStefan Roese #define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1374759dffeSStefan Roese 1384759dffeSStefan Roese #define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM 1394759dffeSStefan Roese #define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 1404759dffeSStefan Roese 1414759dffeSStefan Roese #define SPI_OPMENU_2 SPI_OPCODE_READ 1424759dffeSStefan Roese #define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS 1434759dffeSStefan Roese 1444759dffeSStefan Roese #define SPI_OPMENU_3 SPI_OPCODE_RDSR 1454759dffeSStefan Roese #define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS 1464759dffeSStefan Roese 1474759dffeSStefan Roese #define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT 1484759dffeSStefan Roese #define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 1494759dffeSStefan Roese 1504759dffeSStefan Roese #define SPI_OPMENU_5 SPI_OPCODE_READ_ID 1514759dffeSStefan Roese #define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS 1524759dffeSStefan Roese 1534759dffeSStefan Roese #define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK 1544759dffeSStefan Roese #define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 1554759dffeSStefan Roese 1564759dffeSStefan Roese #define SPI_OPMENU_7 SPI_OPCODE_FAST_READ 1574759dffeSStefan Roese #define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS 1584759dffeSStefan Roese 1594759dffeSStefan Roese #define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN) 1604759dffeSStefan Roese #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ 1614759dffeSStefan Roese (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ 1624759dffeSStefan Roese (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ 1634759dffeSStefan Roese (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) 1644759dffeSStefan Roese #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ 1654759dffeSStefan Roese (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) 1664759dffeSStefan Roese #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ 1674759dffeSStefan Roese (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) 1689eb4339bSBin Meng 1696e670b5cSBin Meng enum ich_version { 1706e670b5cSBin Meng ICHV_7, 1716e670b5cSBin Meng ICHV_9, 1726e670b5cSBin Meng }; 1736e670b5cSBin Meng 1749eb4339bSBin Meng struct ich_spi_platdata { 1756e670b5cSBin Meng enum ich_version ich_version; /* Controller version, 7 or 9 */ 176ab201074SBin Meng bool lockdown; /* lock down controller settings? */ 1771853030eSSimon Glass }; 1789eb4339bSBin Meng 1799eb4339bSBin Meng struct ich_spi_priv { 1809eb4339bSBin Meng int opmenu; 1819eb4339bSBin Meng int menubytes; 1829eb4339bSBin Meng void *base; /* Base of register set */ 1839eb4339bSBin Meng int preop; 1849eb4339bSBin Meng int optype; 1859eb4339bSBin Meng int addr; 1869eb4339bSBin Meng int data; 1879eb4339bSBin Meng unsigned databytes; 1889eb4339bSBin Meng int status; 1899eb4339bSBin Meng int control; 1909eb4339bSBin Meng int bbar; 1919eb4339bSBin Meng int bcr; 1929eb4339bSBin Meng uint32_t *pr; /* only for ich9 */ 1939eb4339bSBin Meng int speed; /* pointer to speed control */ 1949eb4339bSBin Meng ulong max_speed; /* Maximum bus speed in MHz */ 1959eb4339bSBin Meng ulong cur_speed; /* Current bus speed */ 1969eb4339bSBin Meng struct spi_trans trans; /* current transaction in progress */ 1979eb4339bSBin Meng }; 1989eb4339bSBin Meng 1999eb4339bSBin Meng #endif /* _ICH_H_ */ 200