147b43a1fSPaolo Bonzini #ifndef HW_PCNET_H 2175de524SMarkus Armbruster #define HW_PCNET_H 347b43a1fSPaolo Bonzini 447b43a1fSPaolo Bonzini #define PCNET_IOPORT_SIZE 0x20 547b43a1fSPaolo Bonzini #define PCNET_PNPMMIO_SIZE 0x20 647b43a1fSPaolo Bonzini 747b43a1fSPaolo Bonzini #define PCNET_LOOPTEST_CRC 1 847b43a1fSPaolo Bonzini #define PCNET_LOOPTEST_NOCRC 2 947b43a1fSPaolo Bonzini 1047b43a1fSPaolo Bonzini #include "exec/memory.h" 111b53ecd9SMarkus Armbruster #include "hw/irq.h" 1247b43a1fSPaolo Bonzini 1347b43a1fSPaolo Bonzini /* BUS CONFIGURATION REGISTERS */ 1447b43a1fSPaolo Bonzini #define BCR_MSRDA 0 1547b43a1fSPaolo Bonzini #define BCR_MSWRA 1 1647b43a1fSPaolo Bonzini #define BCR_MC 2 1747b43a1fSPaolo Bonzini #define BCR_LNKST 4 1847b43a1fSPaolo Bonzini #define BCR_LED1 5 1947b43a1fSPaolo Bonzini #define BCR_LED2 6 2047b43a1fSPaolo Bonzini #define BCR_LED3 7 2147b43a1fSPaolo Bonzini #define BCR_FDC 9 2247b43a1fSPaolo Bonzini #define BCR_BSBC 18 2347b43a1fSPaolo Bonzini #define BCR_EECAS 19 2447b43a1fSPaolo Bonzini #define BCR_SWS 20 2547b43a1fSPaolo Bonzini #define BCR_PLAT 22 2647b43a1fSPaolo Bonzini 2747b43a1fSPaolo Bonzini #define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000) 2847b43a1fSPaolo Bonzini #define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100) 2947b43a1fSPaolo Bonzini #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080) 3047b43a1fSPaolo Bonzini #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100) 3147b43a1fSPaolo Bonzini #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF) 3247b43a1fSPaolo Bonzini 3347b43a1fSPaolo Bonzini typedef struct PCNetState_st PCNetState; 3447b43a1fSPaolo Bonzini 3547b43a1fSPaolo Bonzini struct PCNetState_st { 3647b43a1fSPaolo Bonzini NICState *nic; 3747b43a1fSPaolo Bonzini NICConf conf; 3847b43a1fSPaolo Bonzini QEMUTimer *poll_timer; 3947b43a1fSPaolo Bonzini int rap, isr, lnkst; 4047b43a1fSPaolo Bonzini uint32_t rdra, tdra; 4147b43a1fSPaolo Bonzini uint8_t prom[16]; 4247b43a1fSPaolo Bonzini uint16_t csr[128]; 4347b43a1fSPaolo Bonzini uint16_t bcr[32]; 4447b43a1fSPaolo Bonzini int xmit_pos; 4547b43a1fSPaolo Bonzini uint64_t timer; 4647b43a1fSPaolo Bonzini MemoryRegion mmio; 4747b43a1fSPaolo Bonzini uint8_t buffer[4096]; 4847b43a1fSPaolo Bonzini qemu_irq irq; 4947b43a1fSPaolo Bonzini void (*phys_mem_read)(void *dma_opaque, hwaddr addr, 5047b43a1fSPaolo Bonzini uint8_t *buf, int len, int do_bswap); 5147b43a1fSPaolo Bonzini void (*phys_mem_write)(void *dma_opaque, hwaddr addr, 5247b43a1fSPaolo Bonzini uint8_t *buf, int len, int do_bswap); 53*4cc76287SMarc-André Lureau DeviceState *dma_opaque; 5447b43a1fSPaolo Bonzini int tx_busy; 5547b43a1fSPaolo Bonzini int looptest; 5647b43a1fSPaolo Bonzini }; 5747b43a1fSPaolo Bonzini 5847b43a1fSPaolo Bonzini void pcnet_h_reset(void *opaque); 5947b43a1fSPaolo Bonzini void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val); 6047b43a1fSPaolo Bonzini uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr); 6147b43a1fSPaolo Bonzini void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val); 6247b43a1fSPaolo Bonzini uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr); 6347b43a1fSPaolo Bonzini uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap); 6447b43a1fSPaolo Bonzini ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_); 6547b43a1fSPaolo Bonzini void pcnet_set_link_status(NetClientState *nc); 664c3b2245SMarkus Armbruster void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info); 6747b43a1fSPaolo Bonzini extern const VMStateDescription vmstate_pcnet; 6847b43a1fSPaolo Bonzini #endif 69