| /openbmc/qemu/tests/tcg/xtensa/ |
| H A D | linker.ld.S | 3 #ifndef XCHAL_VECBASE_RESET_VADDR
4 #define XCHAL_VECBASE_RESET_VADDR XCHAL_WINDOW_VECTORS_VADDR macro
25 ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE
103 .vector.text XCHAL_VECBASE_RESET_VADDR + VECTORS_RESERVED_SIZE :
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| H A D | test_sr.S | 224 movi a2, XCHAL_VECBASE_RESET_VADDR
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| /openbmc/u-boot/include/configs/ |
| H A D | xtfpga.h | 34 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
84 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
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| /openbmc/u-boot/arch/xtensa/include/asm/ |
| H A D | addrspace.h | 27 #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
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| /openbmc/linux/arch/xtensa/include/asm/ |
| H A D | vectors.h | 64 #undef XCHAL_VECBASE_RESET_VADDR
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| /openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| H A D | core.h | 312 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | core-isa.h | 368 #define XCHAL_VECBASE_RESET_VADDR 0x5FFE0400 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | core-isa.h | 392 #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | core-isa.h | 333 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/dc232b/include/variant/ |
| H A D | core.h | 334 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | core-isa.h | 384 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| H A D | core.h | 332 #define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/ |
| H A D | overlay_tool.h | 72 #define XCHAL_VECBASE_RESET_VADDR 0 macro
329 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
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| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | core-isa.h | 383 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| H A D | core.h | 362 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/dc233c/include/variant/ |
| H A D | core.h | 384 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 424 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/de212/include/variant/ |
| H A D | core.h | 488 #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 467 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 466 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | core.h | 466 #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ macro
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| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 467 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 502 #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 523 #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ macro
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| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 605 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ macro
|