1a2e67072SMax Filippov#include "macros.inc" 2efdfac94SMax Filippov 3efdfac94SMax Filippovtest_suite sr 4efdfac94SMax Filippov 59b2d08a0SMax Filippov#if XCHAL_HAVE_BE 69b2d08a0SMax Filippov#define LOW__SR 0x04 79b2d08a0SMax Filippov#define HI_RSR 0x30 89b2d08a0SMax Filippov#define HI_WSR 0x31 99b2d08a0SMax Filippov#define HI_XSR 0x16 109b2d08a0SMax Filippov#else 119b2d08a0SMax Filippov#define LOW__SR 0x40 129b2d08a0SMax Filippov#define HI_RSR 0x03 139b2d08a0SMax Filippov#define HI_WSR 0x13 149b2d08a0SMax Filippov#define HI_XSR 0x61 159b2d08a0SMax Filippov#endif 169b2d08a0SMax Filippov 17efdfac94SMax Filippov.macro sr_op sym, op_sym, op_byte, sr 18efdfac94SMax Filippov .if \sym 19efdfac94SMax Filippov \op_sym a4, \sr 20efdfac94SMax Filippov .else 219b2d08a0SMax Filippov .byte LOW__SR, \sr, \op_byte 22efdfac94SMax Filippov .endif 23efdfac94SMax Filippov.endm 24efdfac94SMax Filippov 25efdfac94SMax Filippov.macro test_sr_op sym, mask, op, op_byte, sr 26efdfac94SMax Filippov movi a4, 0 27efdfac94SMax Filippov .if (\mask) 28efdfac94SMax Filippov set_vector kernel, 0 29efdfac94SMax Filippov sr_op \sym, \op, \op_byte, \sr 30efdfac94SMax Filippov .else 31efdfac94SMax Filippov set_vector kernel, 2f 32efdfac94SMax Filippov1: 33efdfac94SMax Filippov sr_op \sym, \op, \op_byte, \sr 34efdfac94SMax Filippov test_fail 35efdfac94SMax Filippov2: 36efdfac94SMax Filippov reset_ps 37efdfac94SMax Filippov rsr a2, exccause 38efdfac94SMax Filippov assert eqi, a2, 0 39efdfac94SMax Filippov rsr a2, epc1 40efdfac94SMax Filippov movi a3, 1b 41efdfac94SMax Filippov assert eq, a2, a3 42efdfac94SMax Filippov .endif 43efdfac94SMax Filippov.endm 44efdfac94SMax Filippov 45efdfac94SMax Filippov.macro test_sr_mask sr, sym, mask 46efdfac94SMax Filippovtest \sr 479b2d08a0SMax Filippov test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr 489b2d08a0SMax Filippov test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr 499b2d08a0SMax Filippov test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr 50efdfac94SMax Filippovtest_end 51efdfac94SMax Filippov.endm 52efdfac94SMax Filippov 53efdfac94SMax Filippov.macro test_sr sr, conf 54efdfac94SMax Filippov test_sr_mask \sr, \conf, 7 55efdfac94SMax Filippov.endm 56efdfac94SMax Filippov 5750d3a0feSMax Filippov#if XCHAL_HAVE_MAC16 58efdfac94SMax Filippovtest_sr acchi, 1 59efdfac94SMax Filippovtest_sr acclo, 1 6050d3a0feSMax Filippov#else 6150d3a0feSMax Filippovtest_sr_mask /*acchi*/17, 0, 0 6250d3a0feSMax Filippovtest_sr_mask /*acclo*/16, 0, 0 6350d3a0feSMax Filippov#endif 6450d3a0feSMax Filippov 6550d3a0feSMax Filippov#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 6650d3a0feSMax Filippovtest_sr atomctl, 1 6750d3a0feSMax Filippov#else 68efdfac94SMax Filippovtest_sr_mask /*atomctl*/99, 0, 0 6950d3a0feSMax Filippov#endif 7050d3a0feSMax Filippov 7150d3a0feSMax Filippov#if XCHAL_HAVE_BOOLEANS 7250d3a0feSMax Filippovtest_sr br, 1 7350d3a0feSMax Filippov#else 74efdfac94SMax Filippovtest_sr_mask /*br*/4, 0, 0 7550d3a0feSMax Filippov#endif 7650d3a0feSMax Filippov 77efdfac94SMax Filippovtest_sr_mask /*cacheattr*/98, 0, 0 7850d3a0feSMax Filippov 7950d3a0feSMax Filippov#if XCHAL_HAVE_CCOUNT 80efdfac94SMax Filippovtest_sr ccompare0, 1 81efdfac94SMax Filippovtest_sr ccount, 1 8250d3a0feSMax Filippov#else 8350d3a0feSMax Filippovtest_sr_mask /*ccompare0*/240, 0, 0 8450d3a0feSMax Filippovtest_sr_mask /*ccount*/234, 0, 0 8550d3a0feSMax Filippov#endif 8650d3a0feSMax Filippov 8750d3a0feSMax Filippov#if XCHAL_HAVE_CP 88efdfac94SMax Filippovtest_sr cpenable, 1 8950d3a0feSMax Filippov#else 9050d3a0feSMax Filippovtest_sr_mask /*cpenable*/224, 0, 0 9150d3a0feSMax Filippov#endif 9250d3a0feSMax Filippov 9350d3a0feSMax Filippov#if XCHAL_HAVE_DEBUG 9450d3a0feSMax Filippov#if XCHAL_NUM_DBREAK 95efdfac94SMax Filippovtest_sr dbreaka0, 1 96efdfac94SMax Filippovtest_sr dbreakc0, 1 9750d3a0feSMax Filippov#endif 98efdfac94SMax Filippovtest_sr_mask debugcause, 1, 1 9950d3a0feSMax Filippov#else 10050d3a0feSMax Filippovtest_sr_mask /*dbreaka0*/144, 0, 0 10150d3a0feSMax Filippovtest_sr_mask /*dbreakc0*/160, 0, 0 10250d3a0feSMax Filippovtest_sr_mask /*debugcause*/233, 0, 0 10350d3a0feSMax Filippov#endif 10450d3a0feSMax Filippov 105efdfac94SMax Filippovtest_sr depc, 1 10650d3a0feSMax Filippov 10750d3a0feSMax Filippov#if XCHAL_HAVE_PTP_MMU 108efdfac94SMax Filippovtest_sr dtlbcfg, 1 10950d3a0feSMax Filippov#else 11050d3a0feSMax Filippovtest_sr_mask /*dtlbcfg*/92, 0, 0 11150d3a0feSMax Filippov#endif 11250d3a0feSMax Filippov 113efdfac94SMax Filippovtest_sr epc1, 1 11450d3a0feSMax Filippov 11550d3a0feSMax Filippov#if XCHAL_NUM_INTLEVELS > 1 116efdfac94SMax Filippovtest_sr epc2, 1 117efdfac94SMax Filippovtest_sr eps2, 1 11850d3a0feSMax Filippov#else 11950d3a0feSMax Filippovtest_sr_mask /*epc2*/178, 0, 0 12050d3a0feSMax Filippovtest_sr_mask /*eps2*/194, 0, 0 12150d3a0feSMax Filippov#endif 12250d3a0feSMax Filippov 123efdfac94SMax Filippovtest_sr exccause, 1 124efdfac94SMax Filippovtest_sr excsave1, 1 12550d3a0feSMax Filippov 12650d3a0feSMax Filippov#if XCHAL_NUM_INTLEVELS > 1 127efdfac94SMax Filippovtest_sr excsave2, 1 12850d3a0feSMax Filippov#else 12950d3a0feSMax Filippovtest_sr_mask /*excsave2*/210, 0, 0 13050d3a0feSMax Filippov#endif 13150d3a0feSMax Filippov 132efdfac94SMax Filippovtest_sr excvaddr, 1 13350d3a0feSMax Filippov 13450d3a0feSMax Filippov#if XCHAL_HAVE_DEBUG 13550d3a0feSMax Filippov#if XCHAL_NUM_IBREAK 136efdfac94SMax Filippovtest_sr ibreaka0, 1 137efdfac94SMax Filippovtest_sr ibreakenable, 1 13850d3a0feSMax Filippov#endif 139efdfac94SMax Filippovtest_sr icount, 1 140efdfac94SMax Filippovtest_sr icountlevel, 1 14150d3a0feSMax Filippov#else 14250d3a0feSMax Filippovtest_sr_mask /*ibreaka0*/128, 0, 0 14350d3a0feSMax Filippovtest_sr_mask /*ibreakenable*/96, 0, 0 14450d3a0feSMax Filippovtest_sr_mask /*icount*/236, 0, 0 14550d3a0feSMax Filippovtest_sr_mask /*icountlevel*/237, 0, 0 14650d3a0feSMax Filippov#endif 14750d3a0feSMax Filippov 148efdfac94SMax Filippovtest_sr_mask /*intclear*/227, 0, 2 149efdfac94SMax Filippovtest_sr_mask /*interrupt*/226, 0, 3 150efdfac94SMax Filippovtest_sr intenable, 1 15150d3a0feSMax Filippov 15250d3a0feSMax Filippov#if XCHAL_HAVE_PTP_MMU 153efdfac94SMax Filippovtest_sr itlbcfg, 1 15450d3a0feSMax Filippov#else 15550d3a0feSMax Filippovtest_sr_mask /*itlbcfg*/91, 0, 0 15650d3a0feSMax Filippov#endif 15750d3a0feSMax Filippov 15850d3a0feSMax Filippov#if XCHAL_HAVE_LOOPS 159efdfac94SMax Filippovtest_sr lbeg, 1 160efdfac94SMax Filippovtest_sr lcount, 1 161efdfac94SMax Filippovtest_sr lend, 1 16250d3a0feSMax Filippov#else 16350d3a0feSMax Filippovtest_sr_mask /*lbeg*/0, 0, 0 16450d3a0feSMax Filippovtest_sr_mask /*lcount*/2, 0, 0 16550d3a0feSMax Filippovtest_sr_mask /*lend*/1, 0, 0 16650d3a0feSMax Filippov#endif 16750d3a0feSMax Filippov 16850d3a0feSMax Filippov#if XCHAL_HAVE_ABSOLUTE_LITERALS 169efdfac94SMax Filippovtest_sr litbase, 1 17050d3a0feSMax Filippov#else 17150d3a0feSMax Filippovtest_sr_mask /*litbase*/5, 0, 0 17250d3a0feSMax Filippov#endif 17350d3a0feSMax Filippov 17450d3a0feSMax Filippov#if XCHAL_HAVE_MAC16 175efdfac94SMax Filippovtest_sr m0, 1 17650d3a0feSMax Filippov#else 17750d3a0feSMax Filippovtest_sr_mask /*m0*/32, 0, 0 17850d3a0feSMax Filippov#endif 17950d3a0feSMax Filippov 18050d3a0feSMax Filippov#if XCHAL_HW_VERSION >= 250000 18150d3a0feSMax Filippovtest_sr_mask /*memctl*/97, 0, 7 18250d3a0feSMax Filippov#else 183e55239e2SMax Filippovtest_sr_mask /*memctl*/97, 0, 0 18450d3a0feSMax Filippov#endif 18550d3a0feSMax Filippov 18650d3a0feSMax Filippov#if XCHAL_NUM_MISC_REGS 187efdfac94SMax Filippovtest_sr misc0, 1 18850d3a0feSMax Filippov#else 18950d3a0feSMax Filippovtest_sr_mask /*misc0*/244, 0, 0 19050d3a0feSMax Filippov#endif 19150d3a0feSMax Filippov 19250d3a0feSMax Filippov#if XCHAL_HAVE_PREFETCH 19350d3a0feSMax Filippovtest_sr prefctl, 1 19450d3a0feSMax Filippov#else 195efdfac94SMax Filippovtest_sr_mask /*prefctl*/40, 0, 0 19650d3a0feSMax Filippov#endif 19750d3a0feSMax Filippov 19850d3a0feSMax Filippov#if XCHAL_HAVE_PRID 199efdfac94SMax Filippovtest_sr_mask /*prid*/235, 0, 1 20050d3a0feSMax Filippov#else 20150d3a0feSMax Filippovtest_sr_mask /*prid*/235, 0, 0 20250d3a0feSMax Filippov#endif 20350d3a0feSMax Filippov 204efdfac94SMax Filippovtest_sr ps, 1 20550d3a0feSMax Filippov 20650d3a0feSMax Filippov#if XCHAL_HAVE_PTP_MMU 207efdfac94SMax Filippovtest_sr ptevaddr, 1 208efdfac94SMax Filippovtest_sr rasid, 1 20950d3a0feSMax Filippov#else 21050d3a0feSMax Filippovtest_sr_mask /*ptevaddr*/83, 0, 0 21150d3a0feSMax Filippovtest_sr_mask /*rasid*/90, 0, 0 21250d3a0feSMax Filippov#endif 21350d3a0feSMax Filippov 214efdfac94SMax Filippovtest_sr sar, 1 21550d3a0feSMax Filippov 21650d3a0feSMax Filippov#if XCHAL_HAVE_S32C1I 217efdfac94SMax Filippovtest_sr scompare1, 1 21850d3a0feSMax Filippov#else 21950d3a0feSMax Filippovtest_sr_mask /*scompare1*/12, 0, 0 22050d3a0feSMax Filippov#endif 22150d3a0feSMax Filippov 22250d3a0feSMax Filippov#if XCHAL_HAVE_VECBASE 223efdfac94SMax Filippovtest_sr vecbase, 1 224*8164f14bSMax Filippovmovi a2, XCHAL_VECBASE_RESET_VADDR 225*8164f14bSMax Filippovwsr a2, vecbase 22650d3a0feSMax Filippov#else 22750d3a0feSMax Filippovtest_sr_mask /*vecbase*/231, 0, 0 22850d3a0feSMax Filippov#endif 22950d3a0feSMax Filippov 23050d3a0feSMax Filippov#if XCHAL_HAVE_WINDOWED 231efdfac94SMax Filippovtest_sr windowbase, 1 232efdfac94SMax Filippovtest_sr windowstart, 1 23350d3a0feSMax Filippov#else 23450d3a0feSMax Filippovtest_sr_mask /*windowbase*/72, 0, 0 23550d3a0feSMax Filippovtest_sr_mask /*windowstart*/73, 0, 0 23650d3a0feSMax Filippov#endif 237efdfac94SMax Filippov 238efdfac94SMax Filippovtest_suite_end 239