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Searched refs:TRANSCODER_EDP (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c128 MMIO_D(TRANSCONF(TRANSCODER_EDP)); in iterate_generic_mmio()
253 MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP)); in iterate_generic_mmio()
254 MMIO_D(TRANS_HBLANK(TRANSCODER_EDP)); in iterate_generic_mmio()
255 MMIO_D(TRANS_HSYNC(TRANSCODER_EDP)); in iterate_generic_mmio()
256 MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP)); in iterate_generic_mmio()
257 MMIO_D(TRANS_VBLANK(TRANSCODER_EDP)); in iterate_generic_mmio()
258 MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); in iterate_generic_mmio()
259 MMIO_D(BCLRPAT(TRANSCODER_EDP)); in iterate_generic_mmio()
260 MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); in iterate_generic_mmio()
285 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP)); in iterate_generic_mmio()
[all …]
H A Di915_reg.h4637 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c89 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
95 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
407 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
427 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
467 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
491 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
525 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
533 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
547 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
H A Dintel_display_limits.h43 TRANSCODER_EDP, enumerator
H A Dintel_ddi.c445 if (master_transcoder == TRANSCODER_EDP) in bdw_trans_port_sync_master_select()
512 if (cpu_transcoder == TRANSCODER_EDP) { in intel_ddi_transcoder_func_reg_val_get()
713 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) in intel_ddi_connector_get_hw_state()
714 cpu_transcoder = TRANSCODER_EDP; in intel_ddi_connector_get_hw_state()
780 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { in intel_ddi_get_encoder_pipes()
782 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); in intel_ddi_get_encoder_pipes()
986 if (cpu_transcoder == TRANSCODER_EDP) in intel_ddi_enable_transcoder_clock()
1005 if (cpu_transcoder == TRANSCODER_EDP) in intel_ddi_disable_transcoder_clock()
3141 [PORT_A] = TRANSCODER_EDP, in intel_enable_ddi_hdmi()
3595 if (cpu_transcoder == TRANSCODER_EDP) in bdw_transcoder_master_readout()
[all...]
H A Dintel_display_power.h125 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
H A Dintel_psr_regs.h69 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
H A Dintel_pipe_crc.c310 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_crtc_crc_setup_workarounds()
H A Dintel_display.h81 case TRANSCODER_EDP: in transcoder_name()
H A Dintel_display.c1532 if (cpu_transcoder != TRANSCODER_EDP) in hsw_configure_cpu_transcoder()
2456 return transcoder == TRANSCODER_EDP; in intel_cpu_transcoder_has_m2_n2()
2566 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && in intel_set_transcoder_timings()
3479 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); in hsw_panel_transcoders()
3558 return enabled_transcoders & BIT(TRANSCODER_EDP); in has_edp_transcoders()
3569 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | in has_pipe_transcoders()
3777 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && in hsw_get_pipe_config()
H A Dintel_vdsc.c44 if (cpu_transcoder == TRANSCODER_EDP || in is_pipe_dsc()
H A Dintel_backlight.c533 if (cpu_transcoder == TRANSCODER_EDP) in pch_enable_backlight()
H A Dintel_psr.c812 return cpu_transcoder == TRANSCODER_EDP; in transcoder_has_psr2()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c66 if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
198 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { in emulate_monitor_status_change()
286 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= in emulate_monitor_status_change()
H A Dhandlers.c2273 MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()