Searched refs:SOCFPGA_RESET (Results 1 – 11 of 11) sorted by relevance
/openbmc/u-boot/arch/arm/mach-socfpga/ |
H A D | spl_gen5.c | 41 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in spl_boot_device() 45 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); in spl_boot_device() 46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device() 50 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); in spl_boot_device() 159 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); in board_init_f() 160 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f() 161 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); in board_init_f() 193 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
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H A D | spl_a10.c | 41 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in spl_boot_device() 45 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); in spl_boot_device() 46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device() 50 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); in spl_boot_device()
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H A D | spl_s10.c | 128 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); in board_init_f() 129 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); in board_init_f() 136 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); in board_init_f() 145 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
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H A D | misc_gen5.c | 206 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); in arch_early_init_r() 207 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); in arch_early_init_r() 211 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in arch_early_init_r()
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H A D | misc.c | 119 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); in arch_cpu_init() 120 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); in arch_cpu_init()
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H A D | reset_manager_arria10.c | 164 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | in socfpga_per_reset_all() 165 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); in socfpga_per_reset_all()
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H A D | reset_manager_gen5.c | 58 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
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H A D | reset_manager_s10.c | 49 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
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/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
H A D | reset_manager.h | 37 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro
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H A D | reset_manager_s10.h | 112 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro
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/openbmc/u-boot/drivers/ddr/altera/ |
H A D | sdram_s10.c | 199 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); in sdram_mmr_init_full()
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