Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Misc Gen5 fixes
- stratix10 bugfix
- dwmmc bugfix

arm: socfpga: gen5: remove hacked ETH RST handling

The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.

This means we can n

arm: socfpga: gen5: remove hacked ETH RST handling

The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.

This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon

arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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ARM: socfpga: Repair A10 EMAC reset handling

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the

ARM: socfpga: Repair A10 EMAC reset handling

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET

This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut <marex@denx.

ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET

This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arm: socfpga: Add reset driver support for Arria 10

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.c

arm: socfpga: Add reset driver support for Arria 10

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.t

arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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Merge git://git.denx.de/u-boot-socfpga

Conflicts:
include/configs/axs101.h

Signed-off-by: Tom Rini <trini@konsulko.com>

arm: socfpga: Define NAND reset bit

Define the NAND reset bit and fix the ordering of the macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: reset: FIX address of tstscratch register

The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset

arm: socfpga: reset: FIX address of tstscratch register

The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map

Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>

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Merge git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-socfpga

arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits sh

arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

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arm: socfpga: reset: Add SDMMC, QSPI and DMA defines

Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.

Signed-off-by: Marek Vasut <marex@denx

arm: socfpga: reset: Add SDMMC, QSPI and DMA defines

Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <

arm: socfpga: reset: Add function to reset add peripherals

Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function,

arm: socfpga: reset: Replace ad-hoc reset functions

Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
man

arm: socfpga: reset: Implement unified function to toggle reset

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset

arm: socfpga: reset: Start reworking the SoCFPGA reset manager

Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>

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arm: socfpga: reset: Add missing reset manager regs

Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.

Signed-off-by: Marek Vasut <marex@denx.de>

ARM: socfpga: move SoC headers to mach-socfpga/include/mach

Move headers to mach-socfpga as well.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>