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Searched refs:SDRAM (Results 1 – 25 of 152) sorted by relevance

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/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr11 - DDR2-SDRAM 512MB
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
[all …]
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg44 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
48 mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
49 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
50 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
51 mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
52 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
[all …]
/openbmc/u-boot/drivers/ram/
H A DKconfig5 This allows drivers to be provided for SDRAM and other RAM
18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
30 bool "Enable STM32 SDRAM support"
38 bool "Enable MPC83XX SDRAM support"
53 provides an interface to external SDRAM devices. Enabling this
55 SDRAM devices connected to DDR subsystem.
/openbmc/u-boot/board/alliedtelesis/SBx81LIFKW/
H A Dkwbimage.cfg35 DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
36 DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
38 DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
39 DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
40 DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
/openbmc/u-boot/board/alliedtelesis/SBx81LIFXCAT/
H A Dkwbimage.cfg37 DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
38 DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
40 DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
41 DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
42 DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
/openbmc/linux/arch/arm/mach-pxa/
H A Dsleep.S55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
160 @ external accesses after SDRAM is put in self-refresh mode
166 @ put SDRAM into self-refresh
/openbmc/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
7 - interrupts : Should contain the SDRAM ECC IRQ in the
H A Dsocfpga-sdram-controller.txt1 Altera SOCFPGA SDRAM Controller
5 syscon is required by the Altera SOCFPGA SDRAM EDAC.
/openbmc/u-boot/Documentation/devicetree/bindings/ram/
H A Dfsl,mpc83xx-mem-controller.txt77 - activate_to_readwrite: Activate to read/write interval for SDRAM;
155 - sdram_type: Type of SDRAM device to be used; possible values:
198 - sdmode: Initial value loaded into the DDR SDRAM mode
200 - esdmode: Initial value loaded into the DDR SDRAM extended
202 - esdmode2: Initial value loaded into the DDR SDRAM extended
204 - esdmode3: Initial value loaded into the DDR SDRAM extended
235 - bank_bits: Number of bank bits for SDRAM on chip select; possible
238 - row_bits: Number of row bits for SDRAM on chip select; possible values:
240 - col_bits: Number of column bits for SDRAM on chip select; possible
/openbmc/u-boot/doc/
H A DREADME.at9114 0x20000000 - 23FFFFFF SDRAM (64 MB)
36 0x20000000 - 23FFFFFF SDRAM (64 MB)
58 0x20000000 - 23FFFFFF SDRAM (64 MB)
82 0x70000000 - 77FFFFFF SDRAM (128 MB)
98 0x20000000 - 23FFFFFF SDRAM (64 MB)
116 0x20000000 - 27FFFFFF SDRAM (128 MB)
137 0x20000000 - 3FFFFFFF SDRAM (512 MB)
H A DREADME.nand-boot-ppc44021 has to fit into 4kByte. It sets up the CPU and configures the SDRAM
23 loaded from NAND to SDRAM.
29 from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
/openbmc/u-boot/drivers/ddr/altera/
H A DKconfig2 bool "SoCFPGA DDR SDRAM driver"
5 Enable DDR SDRAM controller for the SoCFPGA devices.
/openbmc/u-boot/arch/arm/mach-rockchip/rk3288/
H A DKconfig30 functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
41 functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
50 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
59 includes on-board eMMC and 2GB of SDRAM. Expansion connectors
68 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
77 has 1 or 2 GiB SDRAM. Expansion connectors provide access to
120 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
138 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg88 # SDRAM initalization
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
194 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
200 # with the considered SDRAM internal delay
202 # with the considered SDRAM internal delay
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
209 # with the considered SDRAM internal delay
211 # with the considered SDRAM internal delay
H A Dkwbimage_128M16_1.cfg88 # SDRAM initalization
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
194 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
200 # with the considered SDRAM internal delay
202 # with the considered SDRAM internal delay
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
209 # with the considered SDRAM internal delay
211 # with the considered SDRAM internal delay
/openbmc/u-boot/board/google/
H A DKconfig16 SDRAM. It has a Panther Point platform controller hub, PCIe
37 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Ddmm.txt4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
66 - 1 64-bit DDR4 SDRAM memory controller with ECC
93 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
94 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
136 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
178 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
220 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
221 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
259 b) No 32-bit DDR3 SDRAM memory
289 Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC.
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt52 -rockchip,num-channels: number of SDRAM channels (1 or 2)
53 -rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
93 -rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
103 - rockchip,sdram-params: SDRAM base parameters, in this order:
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dk3-am654-ddrss.txt7 provides an interface to external SDRAM devices. This DDRSS driver
8 adds support for the initialization of the external SDRAM devices by
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dprocessor.hpp50 SDRAM, enumerator
136 {ProcessorMemoryType::SDRAM, "SDRAM"},
H A Dmemory.hpp37 SDRAM, enumerator
140 {MemoryDeviceType::SDRAM, "SDRAM"},
/openbmc/linux/drivers/video/fbdev/omap/
H A DKconfig42 bool "Set DMA SDRAM access priority high"
46 (SDRAM) this will speed up graphics DMA operations.

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