1*3a29afcbSPatrick DelaunayTexas Instruments' K3 AM654 DDRSS 2*3a29afcbSPatrick Delaunay================================= 3*3a29afcbSPatrick Delaunay 4*3a29afcbSPatrick DelaunayK3 based AM654 devices has DDR memory subsystem that comprises 5*3a29afcbSPatrick DelaunaySynopys DDR controller, Synopsis DDR phy and wrapper logic to 6*3a29afcbSPatrick Delaunayintegrate these blocks into the device. This DDR subsystem 7*3a29afcbSPatrick Delaunayprovides an interface to external SDRAM devices. This DDRSS driver 8*3a29afcbSPatrick Delaunayadds support for the initialization of the external SDRAM devices by 9*3a29afcbSPatrick Delaunayconfiguring the DDRSS registers and using the buitin PHY 10*3a29afcbSPatrick Delaunayinitialization routines. 11*3a29afcbSPatrick Delaunay 12*3a29afcbSPatrick DelaunayDDRSS device node: 13*3a29afcbSPatrick Delaunay================== 14*3a29afcbSPatrick DelaunayRequired properties: 15*3a29afcbSPatrick Delaunay-------------------- 16*3a29afcbSPatrick Delaunay- compatible: Shall be: "ti,am654-ddrss" 17*3a29afcbSPatrick Delaunay- reg-names ss - Map the sub system wrapper logic region 18*3a29afcbSPatrick Delaunay ctl - Map the controller region 19*3a29afcbSPatrick Delaunay phy - Map the PHY region 20*3a29afcbSPatrick Delaunay- reg: Contains the register map per reg-names. 21*3a29afcbSPatrick Delaunay- power-domains: Should contain a phandle to a PM domain provider node 22*3a29afcbSPatrick Delaunay and an args specifier containing the DDRSS device id 23*3a29afcbSPatrick Delaunay value. This property is as per the binding, 24*3a29afcbSPatrick Delaunay doc/device-tree-bindings/power/ti,sci-pm-domain.txt 25*3a29afcbSPatrick Delaunay- clocks: Must contain an entry for enabling DDR clock. Should 26*3a29afcbSPatrick Delaunay be defined as per the appropriate clock bindings consumer 27*3a29afcbSPatrick Delaunay usage in doc/device-tree-bindings/clock/ti,sci-clk.txt 28*3a29afcbSPatrick Delaunay 29*3a29afcbSPatrick Delaunay 30*3a29afcbSPatrick DelaunayOptional Properties: 31*3a29afcbSPatrick Delaunay-------------------- 32*3a29afcbSPatrick Delaunay- clock-frequency: Frequency at which DDR pll should be locked. 33*3a29afcbSPatrick Delaunay If not provided, default frequency will be used. 34*3a29afcbSPatrick Delaunay 35*3a29afcbSPatrick DelaunayExample (AM65x): 36*3a29afcbSPatrick Delaunay================ 37*3a29afcbSPatrick Delaunay memory-controller: memory-controller@298e000 { 38*3a29afcbSPatrick Delaunay compatible = "ti,am654-ddrss"; 39*3a29afcbSPatrick Delaunay reg = <0x0298e000 0x200>, 40*3a29afcbSPatrick Delaunay <0x02980000 0x4000>, 41*3a29afcbSPatrick Delaunay <0x02988000 0x2000>; 42*3a29afcbSPatrick Delaunay reg-names = "ss", "ctl", "phy"; 43*3a29afcbSPatrick Delaunay clocks = <&k3_clks 20 0>; 44*3a29afcbSPatrick Delaunay power-domains = <&k3_pds 20>; 45*3a29afcbSPatrick Delaunay u-boot,dm-spl; 46*3a29afcbSPatrick Delaunay }; 47