1*652a49bcSMauro Carvalho Chehab.. SPDX-License-Identifier: GPL-2.0 2*652a49bcSMauro Carvalho Chehab 3*652a49bcSMauro Carvalho Chehab=============================== 4*652a49bcSMauro Carvalho ChehabTI EMIF SDRAM Controller Driver 5*652a49bcSMauro Carvalho Chehab=============================== 6*652a49bcSMauro Carvalho Chehab 7*652a49bcSMauro Carvalho ChehabAuthor 8*652a49bcSMauro Carvalho Chehab====== 9*652a49bcSMauro Carvalho ChehabAneesh V <aneesh@ti.com> 10*652a49bcSMauro Carvalho Chehab 11*652a49bcSMauro Carvalho ChehabLocation 12*652a49bcSMauro Carvalho Chehab======== 13*652a49bcSMauro Carvalho Chehabdriver/memory/emif.c 14*652a49bcSMauro Carvalho Chehab 15*652a49bcSMauro Carvalho ChehabSupported SoCs: 16*652a49bcSMauro Carvalho Chehab=============== 17*652a49bcSMauro Carvalho ChehabTI OMAP44xx 18*652a49bcSMauro Carvalho ChehabTI OMAP54xx 19*652a49bcSMauro Carvalho Chehab 20*652a49bcSMauro Carvalho ChehabMenuconfig option: 21*652a49bcSMauro Carvalho Chehab================== 22*652a49bcSMauro Carvalho ChehabDevice Drivers 23*652a49bcSMauro Carvalho Chehab Memory devices 24*652a49bcSMauro Carvalho Chehab Texas Instruments EMIF driver 25*652a49bcSMauro Carvalho Chehab 26*652a49bcSMauro Carvalho ChehabDescription 27*652a49bcSMauro Carvalho Chehab=========== 28*652a49bcSMauro Carvalho ChehabThis driver is for the EMIF module available in Texas Instruments 29*652a49bcSMauro Carvalho ChehabSoCs. EMIF is an SDRAM controller that, based on its revision, 30*652a49bcSMauro Carvalho Chehabsupports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 31*652a49bcSMauro Carvalho ChehabThis driver takes care of only LPDDR2 memories presently. The 32*652a49bcSMauro Carvalho Chehabfunctions of the driver includes re-configuring AC timing 33*652a49bcSMauro Carvalho Chehabparameters and other settings during frequency, voltage and 34*652a49bcSMauro Carvalho Chehabtemperature changes 35*652a49bcSMauro Carvalho Chehab 36*652a49bcSMauro Carvalho ChehabPlatform Data (see include/linux/platform_data/emif_plat.h) 37*652a49bcSMauro Carvalho Chehab=========================================================== 38*652a49bcSMauro Carvalho ChehabDDR device details and other board dependent and SoC dependent 39*652a49bcSMauro Carvalho Chehabinformation can be passed through platform data (struct emif_platform_data) 40*652a49bcSMauro Carvalho Chehab 41*652a49bcSMauro Carvalho Chehab- DDR device details: 'struct ddr_device_info' 42*652a49bcSMauro Carvalho Chehab- Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck' 43*652a49bcSMauro Carvalho Chehab- Custom configurations: customizable policy options through 44*652a49bcSMauro Carvalho Chehab 'struct emif_custom_configs' 45*652a49bcSMauro Carvalho Chehab- IP revision 46*652a49bcSMauro Carvalho Chehab- PHY type 47*652a49bcSMauro Carvalho Chehab 48*652a49bcSMauro Carvalho ChehabInterface to the external world 49*652a49bcSMauro Carvalho Chehab=============================== 50*652a49bcSMauro Carvalho ChehabEMIF driver registers notifiers for voltage and frequency changes 51*652a49bcSMauro Carvalho Chehabaffecting EMIF and takes appropriate actions when these are invoked. 52*652a49bcSMauro Carvalho Chehab 53*652a49bcSMauro Carvalho Chehab- freq_pre_notify_handling() 54*652a49bcSMauro Carvalho Chehab- freq_post_notify_handling() 55*652a49bcSMauro Carvalho Chehab- volt_notify_handling() 56*652a49bcSMauro Carvalho Chehab 57*652a49bcSMauro Carvalho ChehabDebugfs 58*652a49bcSMauro Carvalho Chehab======= 59*652a49bcSMauro Carvalho ChehabThe driver creates two debugfs entries per device. 60*652a49bcSMauro Carvalho Chehab 61*652a49bcSMauro Carvalho Chehab- regcache_dump : dump of register values calculated and saved for all 62*652a49bcSMauro Carvalho Chehab frequencies used so far. 63*652a49bcSMauro Carvalho Chehab- mr4 : last polled value of MR4 register in the LPDDR2 device. MR4 64*652a49bcSMauro Carvalho Chehab indicates the current temperature level of the device. 65