| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-intc_sar | 7 Specific Absorption Rate (SAR) regulatory mode is typically
11 the current SAR regulatory mode on the Dynamic SAR driver using
14 from the Dynamic SAR driver.
32 This sysfs entry is used to retrieve Dynamic SAR information
33 emitted/maintained by a BIOS that supports Dynamic SAR.
44 level using the Band/Antenna/SAR table index information.
48 given host. The regulatory mode configured on Dynamic SAR
|
| /openbmc/linux/drivers/platform/x86/intel/int1092/ |
| H A D | Kconfig | 7 M.2 modem to regulate the RF power based on SAR data obtained from the
9 to SAR driver. The front end application in userspace will interact with SAR
11 SAR table index and use available communication like MBIM interface to enable
13 given platform needs to support "Dynamic SAR" configuration for a modem available
|
| /openbmc/linux/drivers/dma/ |
| H A D | txx9dmac.h | 72 u64 SAR; /* Source Address Register */ member
82 u32 SAR; member
206 u64 SAR; member
212 u32 SAR; member
|
| H A D | txx9dmac.c | 290 channel64_readq(dc, SAR), in txx9dmac_dump_regs()
302 channel32_readl(dc, SAR), in txx9dmac_dump_regs()
316 channel_writeq(dc, SAR, 0); in txx9dmac_reset_chan()
320 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
474 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR); in txx9dmac_dump_desc()
479 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR, in txx9dmac_dump_desc()
487 d->CHAR, d->SAR, d->DAR, d->CNTR); in txx9dmac_dump_desc()
492 d->CHAR, d->SAR, d->DAR, d->CNTR, in txx9dmac_dump_desc()
755 desc->hwdesc.SAR = src + offset; in txx9dmac_prep_dma_memcpy()
761 desc->hwdesc32.SAR = src + offset; in txx9dmac_prep_dma_memcpy()
[all …]
|
| H A D | idma64.c | 94 channel_writeq(idma64c, SAR, 0); in idma64_chan_start()
|
| /openbmc/linux/arch/sh/include/asm/ |
| H A D | dma-register.h | 14 #define SAR 0x00 /* Source Address Register */ macro
|
| /openbmc/linux/drivers/net/wireless/ath/ath9k/ |
| H A D | Kconfig | 88 TX99 support enables Specific Absorption Rate (SAR) testing.
89 SAR is the unit of measurement for the amount of radio frequency(RF)
91 limits used are expressed in the terms of SAR, which is a measure
96 governmental SAR regulations.
|
| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-rcar.c | 70 #define SAR BIT(0) /* slave addr received */ macro
612 if (ssr_filtered & SAR) { in rcar_i2c_slave_irq()
617 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); in rcar_i2c_slave_irq()
624 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); in rcar_i2c_slave_irq()
628 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); in rcar_i2c_slave_irq()
636 rcar_i2c_write(priv, ICSIER, SAR); in rcar_i2c_slave_irq()
985 rcar_i2c_write(priv, ICSIER, SAR); in rcar_reg_slave()
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-core-clock.txt | 4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
67 - reg : shall be the register address of the Sample-At-Reset (SAR) register
|
| /openbmc/linux/Documentation/hwmon/ |
| H A D | adm1266.rst | 20 integrated 12 bit SAR ADC, accessed using a PMBus interface.
|
| /openbmc/linux/Documentation/translations/zh_CN/arch/parisc/ |
| H A D | registers.rst | 29 CR11 按照ABI的规定（SAR）
|
| /openbmc/u-boot/arch/xtensa/cpu/ |
| H A D | start.S | 421 rsr a2, SAR
483 wsr a2, SAR
|
| /openbmc/linux/drivers/dma/sh/ |
| H A D | shdmac.c | 37 #define SAR 0x00 /* Source Address Register */ macro
216 sh_dmae_writel(sh_chan, hw->sar, SAR); in dmae_set_reg()
459 u32 sar_buf = sh_dmae_readl(sh_chan, SAR); in sh_dmae_desc_completed()
|
| /openbmc/linux/arch/xtensa/kernel/ |
| H A D | coprocessor.S | 179 ssl a3 # SAR: 32 - coprocessor_number
|
| /openbmc/linux/arch/sh/drivers/dma/ |
| H A D | dma-sh.c | 231 __raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR)); in sh_dmac_xfer_dma()
|
| /openbmc/openbmc-test-automation/lib/ |
| H A D | resource.robot | 118 ${SYN_ACK_RESET} SAR
|
| /openbmc/linux/drivers/dma/dw/ |
| H A D | regs.h | 40 DW_REG(SAR); /* Source Address Register */
|
| H A D | core.c | 132 channel_readl(dwc, SAR), in dwc_dump_chan_regs()
161 channel_writel(dwc, SAR, lli_read(desc, sar)); in dwc_do_single_block()
|
| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | sleep44xx.S | 148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
|
| /openbmc/linux/Documentation/arch/parisc/ |
| H A D | registers.rst | 19 CR11 as specified by ABI (SAR)
|
| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-synology-ds414.dts | 72 * pin being sampled at reset (bit 0 of SAR).
|
| H A D | armada-385-clearfog-gtr.dtsi | 50 47 - Control isolation of boot sensitive SAR signals
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-xp-synology-ds414.dts | 159 * pin being sampled at reset (bit 0 of SAR).
|
| /openbmc/qemu/target/xtensa/ |
| H A D | cpu.h | 113 SAR = 3, enumerator
|
| H A D | translate.c | 291 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); in gen_right_shift_sar()
305 tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32); in gen_left_shift_sar()
2277 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2287 tcg_gen_subfi_i32(s, 32, cpu_SR[SAR]); in translate_sll()
2308 tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); in translate_sra()
2334 tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); in translate_srl()
4433 .par = (const uint32_t[]){SAR},
5356 .par = (const uint32_t[]){SAR},
6085 .par = (const uint32_t[]){SAR},
|