1*6a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 2*6a0abce4SKuninori Morimoto * 38b1935e6SGuennadi Liakhovetski * Common header for the legacy SH DMA driver and the new dmaengine driver 48b1935e6SGuennadi Liakhovetski * 58b1935e6SGuennadi Liakhovetski * extracted from arch/sh/include/asm/dma-sh.h: 68b1935e6SGuennadi Liakhovetski * 78b1935e6SGuennadi Liakhovetski * Copyright (C) 2000 Takashi YOSHII 88b1935e6SGuennadi Liakhovetski * Copyright (C) 2003 Paul Mundt 98b1935e6SGuennadi Liakhovetski */ 108b1935e6SGuennadi Liakhovetski #ifndef DMA_REGISTER_H 118b1935e6SGuennadi Liakhovetski #define DMA_REGISTER_H 128b1935e6SGuennadi Liakhovetski 136b32fafeSGeert Uytterhoeven /* DMA registers */ 146b32fafeSGeert Uytterhoeven #define SAR 0x00 /* Source Address Register */ 156b32fafeSGeert Uytterhoeven #define DAR 0x04 /* Destination Address Register */ 166b32fafeSGeert Uytterhoeven #define TCR 0x08 /* Transfer Count Register */ 176b32fafeSGeert Uytterhoeven #define CHCR 0x0C /* Channel Control Register */ 186b32fafeSGeert Uytterhoeven #define DMAOR 0x40 /* DMA Operation Register */ 198b1935e6SGuennadi Liakhovetski 208b1935e6SGuennadi Liakhovetski /* DMAOR definitions */ 216b32fafeSGeert Uytterhoeven #define DMAOR_AE 0x00000004 /* Address Error Flag */ 228b1935e6SGuennadi Liakhovetski #define DMAOR_NMIF 0x00000002 236b32fafeSGeert Uytterhoeven #define DMAOR_DME 0x00000001 /* DMA Master Enable */ 248b1935e6SGuennadi Liakhovetski 258b1935e6SGuennadi Liakhovetski /* Definitions for the SuperH DMAC */ 268b1935e6SGuennadi Liakhovetski #define REQ_L 0x00000000 278b1935e6SGuennadi Liakhovetski #define REQ_E 0x00080000 288b1935e6SGuennadi Liakhovetski #define RACK_H 0x00000000 298b1935e6SGuennadi Liakhovetski #define RACK_L 0x00040000 308b1935e6SGuennadi Liakhovetski #define ACK_R 0x00000000 318b1935e6SGuennadi Liakhovetski #define ACK_W 0x00020000 328b1935e6SGuennadi Liakhovetski #define ACK_H 0x00000000 338b1935e6SGuennadi Liakhovetski #define ACK_L 0x00010000 346b32fafeSGeert Uytterhoeven #define DM_INC 0x00004000 /* Destination addresses are incremented */ 356b32fafeSGeert Uytterhoeven #define DM_DEC 0x00008000 /* Destination addresses are decremented */ 366b32fafeSGeert Uytterhoeven #define DM_FIX 0x0000c000 /* Destination address is fixed */ 376b32fafeSGeert Uytterhoeven #define SM_INC 0x00001000 /* Source addresses are incremented */ 386b32fafeSGeert Uytterhoeven #define SM_DEC 0x00002000 /* Source addresses are decremented */ 396b32fafeSGeert Uytterhoeven #define SM_FIX 0x00003000 /* Source address is fixed */ 408b1935e6SGuennadi Liakhovetski #define RS_IN 0x00000200 418b1935e6SGuennadi Liakhovetski #define RS_OUT 0x00000300 426b32fafeSGeert Uytterhoeven #define RS_AUTO 0x00000400 /* Auto Request */ 436b32fafeSGeert Uytterhoeven #define RS_ERS 0x00000800 /* DMA extended resource selector */ 448b1935e6SGuennadi Liakhovetski #define TS_BLK 0x00000040 458b1935e6SGuennadi Liakhovetski #define TM_BUR 0x00000020 466b32fafeSGeert Uytterhoeven #define CHCR_DE 0x00000001 /* DMA Enable */ 476b32fafeSGeert Uytterhoeven #define CHCR_TE 0x00000002 /* Transfer End Flag */ 486b32fafeSGeert Uytterhoeven #define CHCR_IE 0x00000004 /* Interrupt Enable */ 498b1935e6SGuennadi Liakhovetski 508b1935e6SGuennadi Liakhovetski #endif 51