Home
last modified time | relevance | path

Searched refs:REG32 (Results 1 – 25 of 78) sorted by relevance

1234

/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-cframe-reg.h38 REG32(CRC0, 0x0)
40 REG32(CRC1, 0x4)
41 REG32(CRC2, 0x8)
42 REG32(CRC3, 0xc)
43 REG32(FAR0, 0x10)
47 REG32(FAR1, 0x14)
48 REG32(FAR2, 0x18)
49 REG32(FAR3, 0x1c)
50 REG32(FAR_SFR0, 0x20)
53 REG32(FAR_SFR1, 0x24)
[all …]
H A Dbcm2835_cprman_internals.h32 REG32(CM_PLLA, 0x104)
42 REG32(CM_PLLC, 0x108)
51 REG32(CM_PLLD, 0x10c)
60 REG32(CM_PLLH, 0x110)
64 REG32(CM_PLLB, 0x170)
68 REG32(A2W_PLLA_CTRL, 0x1100)
73 REG32(A2W_PLLC_CTRL, 0x1120)
74 REG32(A2W_PLLD_CTRL, 0x1140)
75 REG32(A2W_PLLH_CTRL, 0x1160)
76 REG32(A2W_PLLB_CTRL, 0x11e0)
[all …]
H A Dxlnx-versal-crl.h19 REG32(ERR_CTRL, 0x0)
21 REG32(IR_STATUS, 0x4)
23 REG32(IR_MASK, 0x8)
25 REG32(IR_ENABLE, 0xc)
27 REG32(IR_DISABLE, 0x10)
29 REG32(WPROT, 0x1c)
31 REG32(PLL_CLK_OTHER_DMN, 0x20)
33 REG32(RPLL_CTRL, 0x40)
40 REG32(RPLL_CFG, 0x44)
46 REG32(RPLL_FRAC_CFG, 0x48)
[all …]
H A Dxlnx-versal-xramc.h20 REG32(XRAM_ERR_CTRL, 0x0)
25 REG32(XRAM_ISR, 0x4)
27 REG32(XRAM_IMR, 0x8)
29 REG32(XRAM_IEN, 0xc)
31 REG32(XRAM_IDS, 0x10)
33 REG32(XRAM_ECC_CNTL, 0x14)
37 REG32(XRAM_CLR_EXE, 0x18)
46 REG32(XRAM_CE_FFA, 0x1c)
48 REG32(XRAM_CE_FFD0, 0x20)
49 REG32(XRAM_CE_FFD1, 0x24)
[all …]
H A Dxlnx-zynqmp-crf.h17 REG32(ERR_CTRL, 0x0)
19 REG32(IR_STATUS, 0x4)
21 REG32(IR_MASK, 0x8)
23 REG32(IR_ENABLE, 0xc)
25 REG32(IR_DISABLE, 0x10)
27 REG32(CRF_WPROT, 0x1c)
29 REG32(APLL_CTRL, 0x20)
37 REG32(APLL_CFG, 0x24)
43 REG32(APLL_FRAC_CFG, 0x28)
49 REG32(DPLL_CTRL, 0x2c)
[all …]
H A Dxlnx-zynqmp-apu-ctrl.h21 REG32(APU_ERR_CTRL, 0x0)
23 REG32(ISR, 0x10)
25 REG32(IMR, 0x14)
27 REG32(IEN, 0x18)
29 REG32(IDS, 0x1c)
31 REG32(CONFIG_0, 0x20)
36 REG32(CONFIG_1, 0x24)
40 REG32(RVBARADDR0L, 0x40)
42 REG32(RVBARADDR0H, 0x44)
44 REG32(RVBARADDR1L, 0x48)
[all …]
H A Dxlnx-versal-cfu.h34 REG32(CFU_ISR, 0x0)
45 REG32(CFU_IMR, 0x4)
56 REG32(CFU_IER, 0x8)
67 REG32(CFU_IDR, 0xc)
78 REG32(CFU_ITR, 0x10)
89 REG32(CFU_PROTECT, 0x14)
91 REG32(CFU_FGCR, 0x18)
107 REG32(CFU_CTL, 0x1c)
124 REG32(CFU_CRAM_RW, 0x20)
129 REG32(CFU_MASK, 0x28)
[all …]
/openbmc/qemu/hw/misc/
H A Dzynq_slcr.c44 REG32(SCL, 0x000)
45 REG32(LOCK, 0x004)
46 REG32(UNLOCK, 0x008)
47 REG32(LOCKSTA, 0x00c)
49 REG32(ARM_PLL_CTRL, 0x100)
50 REG32(DDR_PLL_CTRL, 0x104)
51 REG32(IO_PLL_CTRL, 0x108)
58 REG32(PLL_STATUS, 0x10c)
59 REG32(ARM_PLL_CFG, 0x110)
60 REG32(DDR_PLL_CFG, 0x114)
[all …]
H A Dxlnx-versal-pmc-iou-slcr.c40 REG32(MIO_PIN_0, 0x0)
45 REG32(MIO_PIN_1, 0x4)
50 REG32(MIO_PIN_2, 0x8)
55 REG32(MIO_PIN_3, 0xc)
60 REG32(MIO_PIN_4, 0x10)
65 REG32(MIO_PIN_5, 0x14)
70 REG32(MIO_PIN_6, 0x18)
75 REG32(MIO_PIN_7, 0x1c)
80 REG32(MIO_PIN_8, 0x20)
85 REG32(MIO_PIN_9, 0x24)
[all …]
H A Diotkit-secctl.c26 REG32(SECRESPCFG, 0x10)
27 REG32(NSCCFG, 0x14)
28 REG32(SECMPCINTSTATUS, 0x1c)
29 REG32(SECPPCINTSTAT, 0x20)
30 REG32(SECPPCINTCLR, 0x24)
31 REG32(SECPPCINTEN, 0x28)
32 REG32(SECMSCINTSTAT, 0x30)
33 REG32(SECMSCINTCLR, 0x34)
34 REG32(SECMSCINTEN, 0x38)
35 REG32(BRGINTSTAT, 0x40)
[all …]
H A Darmsse-mhu.c29 REG32(CPU0INTR_STAT, 0x0)
30 REG32(CPU0INTR_SET, 0x4)
31 REG32(CPU0INTR_CLR, 0x8)
32 REG32(CPU1INTR_STAT, 0x10)
33 REG32(CPU1INTR_SET, 0x14)
34 REG32(CPU1INTR_CLR, 0x18)
35 REG32(PID4, 0xfd0)
36 REG32(PID5, 0xfd4)
37 REG32(PID6, 0xfd8)
38 REG32(PID7, 0xfdc)
[all …]
H A Diotkit-sysinfo.c31 REG32(SYS_VERSION, 0x0)
32 REG32(SYS_CONFIG, 0x4)
33 REG32(SYS_CONFIG1, 0x8)
34 REG32(IIDR, 0xfc8)
35 REG32(PID4, 0xfd0)
36 REG32(PID5, 0xfd4)
37 REG32(PID6, 0xfd8)
38 REG32(PID7, 0xfdc)
39 REG32(PID0, 0xfe0)
40 REG32(PID1, 0xfe4)
[all …]
H A Darmsse-cpuid.c31 REG32(CPUID, 0x0)
32 REG32(PID4, 0xfd0)
33 REG32(PID5, 0xfd4)
34 REG32(PID6, 0xfd8)
35 REG32(PID7, 0xfdc)
36 REG32(PID0, 0xfe0)
37 REG32(PID1, 0xfe4)
38 REG32(PID2, 0xfe8)
39 REG32(PID3, 0xfec)
40 REG32(CID0, 0xff0)
[all …]
H A Darmsse-cpu-pwrctrl.c28 REG32(CPUPWRCFG, 0x0)
29 REG32(PID4, 0xfd0)
30 REG32(PID5, 0xfd4)
31 REG32(PID6, 0xfd8)
32 REG32(PID7, 0xfdc)
33 REG32(PID0, 0xfe0)
34 REG32(PID1, 0xfe4)
35 REG32(PID2, 0xfe8)
36 REG32(PID3, 0xfec)
37 REG32(CID0, 0xff0)
[all …]
H A Dxlnx-versal-trng.c44 REG32(INT_CTRL, 0x0)
51 REG32(STATUS, 0x4)
57 REG32(CTRL, 0x8)
69 REG32(CTRL_2, 0xc)
73 REG32(CTRL_3, 0x10)
76 REG32(CTRL_4, 0x14)
78 REG32(EXT_SEED_0, 0x40)
79 REG32(EXT_SEED_1, 0x44)
80 REG32(EXT_SEED_2, 0x48)
81 REG32(EXT_SEED_3, 0x4c)
[all …]
H A Diotkit-sysctl.c34 REG32(SECDBGSTAT, 0x0)
35 REG32(SECDBGSET, 0x4)
36 REG32(SECDBGCLR, 0x8)
37 REG32(SCSECCTRL, 0xc)
38 REG32(FCLK_DIV, 0x10)
39 REG32(SYSCLK_DIV, 0x14)
40 REG32(CLOCK_FORCE, 0x18)
41 REG32(RESET_SYNDROME, 0x100)
42 REG32(RESET_MASK, 0x104)
43 REG32(SWRESET, 0x108)
[all …]
/openbmc/qemu/include/hw/char/
H A Dnrf51_uart.h25 REG32(UART_STARTRX, 0x000)
26 REG32(UART_STOPRX, 0x004)
27 REG32(UART_STARTTX, 0x008)
28 REG32(UART_STOPTX, 0x00C)
29 REG32(UART_SUSPEND, 0x01C)
31 REG32(UART_CTS, 0x100)
32 REG32(UART_NCTS, 0x104)
33 REG32(UART_RXDRDY, 0x108)
34 REG32(UART_TXDRDY, 0x11C)
35 REG32(UART_ERROR, 0x124)
[all …]
/openbmc/qemu/include/hw/i2c/
H A Daspeed_i2c.h69 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */
70 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */
71 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */
74 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */
77 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */
92 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */
93 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */
94 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */
95 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */
114 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
[all …]
/openbmc/qemu/include/hw/rtc/
H A Dxlnx-zynqmp-rtc.h38 REG32(SET_TIME_WRITE, 0x0)
39 REG32(SET_TIME_READ, 0x4)
40 REG32(CALIB_WRITE, 0x8)
44 REG32(CALIB_READ, 0xc)
48 REG32(CURRENT_TIME, 0x10)
49 REG32(CURRENT_TICK, 0x14)
51 REG32(ALARM, 0x18)
52 REG32(RTC_INT_STATUS, 0x20)
55 REG32(RTC_INT_MASK, 0x24)
58 REG32(RTC_INT_EN, 0x28)
[all …]
/openbmc/qemu/hw/net/
H A Dcadence_gem.c48 REG32(NWCTRL, 0x0) /* Network Control reg */
81 REG32(NWCFG, 0x4) /* Network Config reg */
111 REG32(NWSTATUS, 0x8) /* Network Status reg */
112 REG32(USERIO, 0xc) /* User IO reg */
114 REG32(DMACFG, 0x10) /* DMA Control reg */
134 REG32(TXSTATUS, 0x14) /* TX Status reg */
149 REG32(RXQBASE, 0x18) /* RX Q Base address reg */
150 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
151 REG32(RXSTATUS, 0x20) /* RX Status reg */
159 REG32(ISR, 0x24) /* Interrupt Status reg */
[all …]
/openbmc/qemu/hw/usb/
H A Dhcd-dwc3.c47 REG32(GSBUSCFG0, 0x00)
64 REG32(GSBUSCFG1, 0x04)
69 REG32(GTXTHRCFG, 0x08)
80 REG32(GRXTHRCFG, 0x0c)
90 REG32(GCTL, 0x10)
106 REG32(GPMSTS, 0x14)
107 REG32(GSTS, 0x18)
120 REG32(GUCTL1, 0x1c)
122 REG32(GSNPSID, 0x20)
123 REG32(GGPIO, 0x24)
[all …]
/openbmc/qemu/include/hw/acpi/
H A Dtpm.h137 REG32(CRB_LOC_STATE, 0x00)
143 REG32(CRB_LOC_CTRL, 0x08)
144 REG32(CRB_LOC_STS, 0x0C)
147 REG32(CRB_INTF_ID, 0x30)
161 REG32(CRB_INTF_ID2, 0x34)
164 REG32(CRB_CTRL_EXT, 0x38)
165 REG32(CRB_CTRL_REQ, 0x40)
166 REG32(CRB_CTRL_STS, 0x44)
169 REG32(CRB_CTRL_CANCEL, 0x48)
170 REG32(CRB_CTRL_START, 0x4C)
[all …]
/openbmc/qemu/hw/nvram/
H A Dxlnx-zynqmp-efuse.c40 REG32(WR_LOCK, 0x0)
42 REG32(CFG, 0x4)
47 REG32(STATUS, 0x8)
55 REG32(EFUSE_PGM_ADDR, 0xc)
59 REG32(EFUSE_RD_ADDR, 0x10)
62 REG32(EFUSE_RD_DATA, 0x14)
63 REG32(TPGM, 0x18)
65 REG32(TRD, 0x1c)
67 REG32(TSU_H_PS, 0x20)
69 REG32(TSU_H_PS_CS, 0x24)
[all …]
/openbmc/qemu/include/hw/cxl/
H A Dcxl_component.h43 REG32(CXL_CAPABILITY_HEADER, 0)
50 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \
71 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET)
88 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
89 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
90 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
98 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
99 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
103 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
125 REG32(CXL_HDM_DECODER##n##_BASE_LO, \
[all …]
/openbmc/qemu/hw/timer/
H A Dcmsdk-apb-dualtimer.c32 REG32(TIMER1LOAD, 0x0)
33 REG32(TIMER1VALUE, 0x4)
34 REG32(TIMER1CONTROL, 0x8)
44 REG32(TIMER1INTCLR, 0xc)
45 REG32(TIMER1RIS, 0x10)
46 REG32(TIMER1MIS, 0x14)
47 REG32(TIMER1BGLOAD, 0x18)
48 REG32(TIMER2LOAD, 0x20)
49 REG32(TIMER2VALUE, 0x24)
50 REG32(TIMER2CONTROL, 0x28)
[all …]

1234