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Searched refs:PRV_S (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dop_helper.c143 (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || in check_zicbo_envcfg()
144 ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { in check_zicbo_envcfg()
148 if ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)) { in check_zicbo_envcfg()
267 if (!(env->priv >= PRV_S)) { in helper_sret()
378 bool prv_s = env->priv == PRV_S; in helper_wfi()
395 if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && in helper_wrs_nto()
409 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) { in helper_tlb_flush()
434 (env->priv == PRV_S && !env->virt_enabled)) { in helper_hyp_tlb_flush()
444 if (env->priv == PRV_S && !env->virt_enabled && in helper_hyp_gvma_tlb_flush()
463 if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { in check_access_hlsv()
H A Dpmu.c114 (env->priv == PRV_S && virt_on && in riscv_pmu_incr_ctr_rv32()
118 (env->priv == PRV_S && !virt_on && in riscv_pmu_incr_ctr_rv32()
155 (env->priv == PRV_S && virt_on && in riscv_pmu_incr_ctr_rv64()
159 (env->priv == PRV_S && !virt_on && in riscv_pmu_incr_ctr_rv64()
207 g_assert(env->priv <= PRV_S); in riscv_pmu_icount_update_priv()
216 g_assert(newpriv <= PRV_S); in riscv_pmu_icount_update_priv()
247 g_assert(env->priv <= PRV_S); in riscv_pmu_cycle_update_priv()
256 g_assert(newpriv <= PRV_S); in riscv_pmu_cycle_update_priv()
H A Dcpu_helper.c58 if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { in riscv_env_mmu_index()
81 case PRV_S: in cpu_get_fcfien()
110 case PRV_S: in cpu_get_bcfien()
242 case PRV_S: in riscv_cpu_update_mask()
512 vsie = (env->priv < PRV_S) || in riscv_cpu_local_irq_pending()
513 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); in riscv_cpu_local_irq_pending()
517 hsie = (env->priv < PRV_S) || in riscv_cpu_local_irq_pending()
518 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); in riscv_cpu_local_irq_pending()
1052 MMU_DATA_LOAD, PRV_S); in get_physical_address()
1187 } else if (mode != PRV_S) { in get_physical_address()
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H A Dinternals.h47 ret = PRV_S; in mmuidx_priv()
H A Dcsr.c512 if (env->priv == PRV_S && !env->virt_enabled && in satp()
516 if (env->priv == PRV_S && env->virt_enabled && in satp()
526 if (env->priv == PRV_S && !env->virt_enabled && in hgatp()
631 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { in seed()
1082 curr_val += counter_arr[PRV_S]; in riscv_pmu_ctr_get_fixed_counters_val()
1090 curr_val += counter_arr_virt[PRV_S]; in riscv_pmu_ctr_get_fixed_counters_val()
1580 case PRV_S: in legalize_mpp()
2072 if (env->priv == PRV_S && env->mvien & MIP_SEIP && in rmw_xireg()
2079 priv = PRV_S; in rmw_xireg()
2084 priv = PRV_S; in rmw_xireg()
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H A Dgdbstub.c231 env->priv = PRV_S; in riscv_gdb_set_virtual()
H A Dcpu_bits.h622 #define PRV_S 1 macro
/openbmc/qemu/hw/intc/
H A Driscv_imsic.c219 if (priv == PRV_S) { in riscv_imsic_rmw()
384 riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, in riscv_imsic_realize()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h65 #define PRV_S 1 macro