Home
last modified time | relevance | path

Searched refs:PACKET3_WAIT_REG_MEM (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h209 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dsoc15d.h141 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dnvd.h116 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dvid.h168 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dcikd.h287 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dgfx_v7_0.c2082 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
3141 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_pipeline_sync()
3184 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
H A Dsid.h1719 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dgfx_v6_0.c2271 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync()
2298 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush()
H A Dgfx_v8_0.c6063 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_hdp_flush()
6194 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_pipeline_sync()
6213 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_vm_flush()
H A Dgfx_v9_4_3.c230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_4_3_wait_reg_mem()
H A Dgfx_v11_0.c304 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
H A Dgfx_v9_0.c977 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
H A Dgfx_v10_0.c3749 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v10_0_wait_reg_mem()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h1194 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dr600_cs.c843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()
1751 case PACKET3_WAIT_REG_MEM: in r600_packet3_check()
H A Dsid.h1656 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dcikd.h1755 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dsi.c4568 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_gfx_check()
4671 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_compute_check()
5110 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
H A Devergreen_cs.c2085 case PACKET3_WAIT_REG_MEM: in evergreen_packet3_check()
3388 case PACKET3_WAIT_REG_MEM: in evergreen_vm_packet3_check()
H A Devergreend.h1578 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dr600d.h1615 #define PACKET3_WAIT_REG_MEM 0x3C macro
H A Dni.c2691 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
H A Dcik.c3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
5733 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()