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Searched refs:PACKET3_SET_CONFIG_REG (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h259 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dsoc15d.h293 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dnvd.h318 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dvid.h339 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dcikd.h457 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dgfx_v6_0.c1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
H A Dsid.h1845 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dgfx_v7_0.c2245 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v7_0_ring_emit_ib_compute()
H A Dgfx_v9_4_3.c2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v9_4_3_ring_emit_ib_compute()
H A Dgfx_v11_0.c5342 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v11_0_ring_emit_ib_compute()
H A Dgfx_v8_0.c6136 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v8_0_ring_emit_ib_compute()
H A Dgfx_v9_0.c5275 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v9_0_ring_emit_ib_compute()
H A Dgfx_v10_0.c8347 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v10_0_ring_emit_ib_compute()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dr600.c2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2902 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2991 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
3011 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
3373 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_ib_execute()
3415 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in r600_ib_test()
H A Dnid.h1269 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dsid.h1782 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dcikd.h1925 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dsi.c3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3415 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
4620 case PACKET3_SET_CONFIG_REG: in si_vm_packet3_gfx_check()
H A Devergreen_cs.c2299 case PACKET3_SET_CONFIG_REG: in evergreen_packet3_check()
3420 case PACKET3_SET_CONFIG_REG: in evergreen_vm_packet3_check()
H A Devergreend.h1665 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dr600d.h1686 #define PACKET3_SET_CONFIG_REG 0x68 macro
H A Dni.c1425 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
H A Dr600_cs.c1908 case PACKET3_SET_CONFIG_REG: in r600_packet3_check()
H A Devergreen.c2943 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()