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Searched refs:MXL_RV32 (Results 1 – 24 of 24) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtranslate.c132 #define get_xl(ctx) MXL_RV32
140 #define get_address_xl(ctx) MXL_RV32
157 #define get_ol(ctx) MXL_RV32
169 #define get_xl_max(ctx) MXL_RV32
230 if (get_xl(ctx) == MXL_RV32) { in gen_pc_plus_diff()
234 if (get_xl(ctx) == MXL_RV32) { in gen_pc_plus_diff()
339 case MXL_RV32: in get_gpr()
393 case MXL_RV32: in gen_set_gpr()
414 case MXL_RV32: in gen_set_gpri()
450 case MXL_RV32: in get_fpr_hs()
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H A Dcpu.h642 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
676 if (xl != MXL_RV32) { in cpu_get_xl()
693 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
706 #define cpu_address_xl(env) ((void)(env), MXL_RV32)
726 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
733 if (env->misa_mxl != MXL_RV32) { in riscv_cpu_sxl()
737 return MXL_RV32; in riscv_cpu_sxl()
H A Dcsr.c113 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; in ctr()
164 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32()
214 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { in mctr()
232 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32()
250 if (riscv_cpu_mxl(env) != MXL_RV32) { in sscofpmf_32()
268 if (riscv_cpu_mxl(env) != MXL_RV32) { in smcntrpmf_32()
282 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32()
319 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32()
355 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32()
374 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32()
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H A Dcpu.c60 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_is_32bit()
416 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in set_satp_mode_max_supported()
455 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? in riscv_max_cpu_init()
886 if (env->xl == MXL_RV32) { in riscv_cpu_set_pc()
899 if (env->xl == MXL_RV32) { in riscv_cpu_get_pc()
945 if (env->misa_mxl > MXL_RV32) { in riscv_cpu_reset_hold()
1045 case MXL_RV32: in riscv_cpu_disas_set_info()
1236 if (cpu->env.misa_mxl == MXL_RV32) { in riscv_add_satp_mode_properties()
1427 case MXL_RV32: in riscv_cpu_validate_misa_mxl()
2171 case MXL_RV32: in prop_marchid_set()
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H A Dpmu.c296 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr()
428 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_is_of_set()
444 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_set_of_if_clear()
497 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
H A Dgdbstub.c66 case MXL_RV32: in riscv_cpu_gdb_read_register()
86 case MXL_RV32: in riscv_cpu_gdb_write_register()
348 case MXL_RV32: in riscv_cpu_register_gdb_regs_for_features()
H A Dmonitor.c156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx()
225 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
H A Ddebug.c81 case MXL_RV32: in extract_trigger_type()
137 case MXL_RV32: in build_tdata1()
185 case MXL_RV32: in tdata1_validate()
228 case MXL_RV32: in textra_validate()
264 case MXL_RV32: in textra_validate()
379 case MXL_RV32: in trigger_textra_match()
H A Dcommon-semi-target.h35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
H A Dcpu_helper.c130 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; in cpu_get_tb_cpu_state()
259 if (xl == MXL_RV32) { in riscv_cpu_update_mask()
928 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
936 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
946 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1057 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1067 if (riscv_cpu_sxl(env) == MXL_RV32) { in get_physical_address()
1241 if (riscv_cpu_sxl(env) == MXL_RV32) { in get_physical_address()
H A Dcpu_bits.h574 MXL_RV32 = 1, enumerator
H A Dop_helper.c64 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzacas.c.inc35 assert(get_ol(ctx) == MXL_RV32);
48 assert(get_ol(ctx) == MXL_RV32);
90 case MXL_RV32:
H A Dtrans_rvi.c.inc105 if (get_xl(ctx) == MXL_RV32) {
747 ctx->ol = MXL_RV32;
754 ctx->ol = MXL_RV32;
761 ctx->ol = MXL_RV32;
768 ctx->ol = MXL_RV32;
796 ctx->ol = MXL_RV32;
803 ctx->ol = MXL_RV32;
810 ctx->ol = MXL_RV32;
817 ctx->ol = MXL_RV32;
824 ctx->ol = MXL_RV32;
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H A Dtrans_rvm.c.inc326 ctx->ol = MXL_RV32;
334 ctx->ol = MXL_RV32;
342 ctx->ol = MXL_RV32;
350 ctx->ol = MXL_RV32;
358 ctx->ol = MXL_RV32;
H A Dtrans_rvb.c.inc385 ctx->ol = MXL_RV32;
393 ctx->ol = MXL_RV32;
401 ctx->ol = MXL_RV32;
409 ctx->ol = MXL_RV32;
417 ctx->ol = MXL_RV32;
H A Dtrans_rvzce.c.inc178 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
223 MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ;
H A Dtrans_xthead.c.inc153 ctx->ol = MXL_RV32;
515 ctx->ol = MXL_RV32;
524 ctx->ol = MXL_RV32;
539 ctx->ol = MXL_RV32;
548 ctx->ol = MXL_RV32;
H A Dtrans_rvd.c.inc28 if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \
56 if (get_xl_max(ctx) == MXL_RV32) {
80 if (get_xl_max(ctx) == MXL_RV32) {
H A Dtrans_rvv.c.inc303 if (get_xl(s) == MXL_RV32) {
2046 if (get_xl(s) == MXL_RV32 && s->sew == MO_64) {
/openbmc/qemu/linux-user/riscv/
H A Dtarget_proc.h19 mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; in open_cpuinfo()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c103 if (xl == MXL_RV32) { in riscv_cpu_synchronize_from_tb()
126 if (xl == MXL_RV32) { in riscv_restore_state_to_opc()
558 if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
864 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in cpu_enable_zc_implied_rules()
873 if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) { in cpu_enable_zc_implied_rules()
1402 if (env->misa_mxl != MXL_RV32) { in riscv_init_max_cpu_extensions()
/openbmc/qemu/hw/riscv/
H A Dboot.c40 return mcc->misa_mxl_max == MXL_RV32; in riscv_is_32bit()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c67 case MXL_RV32: in kvm_riscv_reg_id_ulong()
1467 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { in kvm_riscv_handle_sbi_dbcn()
1990 mcc->misa_mxl_max = MXL_RV32; in riscv_host_cpu_class_init()