Searched refs:MV_DDR_TIM_DEFAULT (Results 1 – 7 of 7) sorted by relevance
68 MV_DDR_TIM_DEFAULT} }, /* timing */
69 MV_DDR_TIM_DEFAULT} }, /* timing */
67 MV_DDR_TIM_DEFAULT} }, /* timing */
90 MV_DDR_TIM_DEFAULT} }, /* timing */
66 MV_DDR_TIM_DEFAULT} }, /* timing */
110 MV_DDR_TIM_DEFAULT, enumerator
594 } else if (timing != MV_DDR_TIM_DEFAULT) { in hws_ddr3_tip_init_controller()1354 } else if (timing != MV_DDR_TIM_DEFAULT) { in ddr3_tip_freq_set()