1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
4 * based on board/solidrun/clearfog/clearfog.c
5 */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <miiphy.h>
10 #include <netdev.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include <../serdes/a38x/high_speed_env_spec.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /*
21 * Those values and defines are taken from the Marvell U-Boot version
22 * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
23 */
24 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
25 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
26
27 #define BOARD_GPP_OUT_VAL_LOW 0x0
28 #define BOARD_GPP_OUT_VAL_MID 0x0
29 #define BOARD_GPP_POL_LOW 0x0
30 #define BOARD_GPP_POL_MID 0x0
31
32 static struct serdes_map board_serdes_map[] = {
33 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
34 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
35 {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
36 {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
37 {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
38 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
39 };
40
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)41 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
42 {
43 *serdes_map_array = board_serdes_map;
44 *count = ARRAY_SIZE(board_serdes_map);
45 return 0;
46 }
47
48 /*
49 * Define the DDR layout / topology here in the board file. This will
50 * be used by the DDR3 init code in the SPL U-Boot version to configure
51 * the DDR3 controller.
52 */
53 static struct mv_ddr_topology_map board_topology_map = {
54 DEBUG_LEVEL_ERROR,
55 0x1, /* active interfaces */
56 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
57 { { { {0x1, 0, 0, 0},
58 {0x1, 0, 0, 0},
59 {0x1, 0, 0, 0},
60 {0x1, 0, 0, 0},
61 {0x1, 0, 0, 0} },
62 SPEED_BIN_DDR_1600K, /* speed_bin */
63 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
64 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
65 MV_DDR_FREQ_800, /* frequency */
66 0, 0, /* cas_wl cas_l */
67 MV_DDR_TEMP_LOW, /* temperature */
68 MV_DDR_TIM_DEFAULT} }, /* timing */
69 BUS_MASK_32BIT_ECC, /* Busses mask */
70 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
71 { {0} }, /* raw spd data */
72 {0} /* timing parameters */
73 };
74
mv_ddr_topology_map_get(void)75 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
76 {
77 /* Return the board topology as defined in the board code */
78 return &board_topology_map;
79 }
80
board_early_init_f(void)81 int board_early_init_f(void)
82 {
83 /* Configure MPP */
84 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
85 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
86 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
87 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
88 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
89 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
90 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
91 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
92
93 /* Set GPP Out value */
94 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
95 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
96
97 /* Set GPP Polarity */
98 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
99 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
100
101 /* Set GPP Out Enable */
102 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
103 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
104
105 return 0;
106 }
107
board_init(void)108 int board_init(void)
109 {
110 /* Address of boot parameters */
111 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
112
113 return 0;
114 }
115
checkboard(void)116 int checkboard(void)
117 {
118 puts("Board: Helios4\n");
119
120 return 0;
121 }
122
board_eth_init(bd_t * bis)123 int board_eth_init(bd_t *bis)
124 {
125 cpu_eth_init(bis); /* Built in controller(s) come first */
126 return pci_eth_init(bis);
127 }
128