Home
last modified time | relevance | path

Searched refs:M1 (Results 1 – 25 of 125) sorted by relevance

12345

/openbmc/u-boot/board/intel/cherryhill/
H A Dcherryhill.c20 GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
23 GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
26 GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
[all …]
/openbmc/u-boot/board/ti/dra7xx/
H A Dmux_data.h43 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
44 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
45 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
46 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
47 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
48 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
49 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
50 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
51 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
52 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
[all …]
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dmux.c53 {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */
54 {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */
55 {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */
56 {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */
57 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */
68 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */
69 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */
70 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */
71 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */
72 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */
[all …]
/openbmc/u-boot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
22 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
23 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
25 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
/openbmc/u-boot/board/ti/am57xx/
H A Dmux_data.h50 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
51 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
52 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
53 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
54 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
55 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
56 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
57 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
58 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
59 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
[all …]
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h21 { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
22 { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
23 { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
24 { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
25 { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
26 { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
27 { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
28 { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
29 { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
30 { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
/openbmc/u-boot/board/ti/panda/
H A Dpanda_mux_data.h17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
26 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2() local
68 if ((ctrl & 0x80000000) && M1) { in read_pll_2()
69 khz = ref * N1 / M1; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
162 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
171 &N1, &M1, NULL, NULL, &log2P); in nv40_clk_calc()
[all …]
H A Dpllnv04.c151 int M1, N1, M2, N2, log2P; in getMNP_double() local
164 for (M1 = minM1; M1 <= maxM1; M1++) { in getMNP_double()
165 if (crystal/M1 < minU1) in getMNP_double()
167 if (crystal/M1 > maxU1) in getMNP_double()
171 calcclk1 = crystal * N1 / M1; in getMNP_double()
212 *pM1 = M1; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
H A Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
40 pv->M1 = M1; in nv04_clk_pll_calc()
/openbmc/linux/Documentation/i2c/
H A Di2c-topology.rst63 '--------' | | mux M1 |--. .--------.
72 2. M1 locks muxes on its parent (the root adapter in this case).
73 3. M1 calls ->select to ready the mux.
74 4. M1 (presumably) does some I2C transfers as part of its select.
77 5. M1 feeds the I2C transfer from step 1 to its parent adapter as a
79 6. M1 calls ->deselect, if it has one.
81 8. M1 unlocks muxes on its parent.
142 '--------' | | mux M1 |--. .--------.
151 2. M1 locks muxes on its parent (the root adapter in this case).
152 3. M1 locks its parent adapter.
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv50.c41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
69 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
73 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
H A Dnv04.c164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
376 pv.M1 = M1; in nv04_devinit_pll_set()
/openbmc/linux/arch/arm64/crypto/
H A Dpolyval-ce-core.S39 M1 .req v1 label
223 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
256 karatsuba1 M1 KEY7
278 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
281 karatsuba1 M1 KEY7
287 ld1 {M0.16b, M1.16b}, [MSG], #32
290 karatsuba1 M1 KEY7
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv40.c40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
57 ram->coef = (N1 << 8) | M1; in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h110 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
111 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
205 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
206 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
207 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
208 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
218 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
219 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
220 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
221 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
[all …]
/openbmc/linux/arch/arm64/boot/dts/apple/
H A Dt6001-j375c.dts3 * Mac Studio (M1 Max, 2022)
17 model = "Apple Mac Studio (M1 Max, 2022)";
H A Dt6000-j316s.dts3 * MacBook Pro (16-inch, M1 Pro, 2021)
17 model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)";
H A Dt6001-j314c.dts3 * MacBook Pro (14-inch, M1 Max, 2021)
17 model = "Apple MacBook Pro (14-inch, M1 Max, 2021)";
H A Dt6000-j314s.dts3 * MacBook Pro (14-inch, M1 Pro, 2021)
17 model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)";
H A Dt6001-j316c.dts3 * MacBook Pro (16-inch, M1 Max, 2021)
17 model = "Apple MacBook Pro (16-inch, M1 Max, 2021)";
H A Dt8103-jxxx.dtsi3 * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021)
5 * This file contains parts common to all Apple M1 devices using the t8103.
H A Dt8103-j313.dts3 * Apple MacBook Air (M1, 2020)
18 model = "Apple MacBook Air (M1, 2020)";
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv6m/
H A Dtune-cortexm1.inc2 # Tune Settings for Cortex-M1
6 TUNEVALID[cortexm1] = "Enable Cortex-M1 specific processor optimizations"
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dpll.h9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;

12345