Home
last modified time | relevance | path

Searched refs:ISELECT_IMSIC_EIDELIVERY (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h858 #define ISELECT_IMSIC_EIDELIVERY 0x70 macro
864 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY
H A Dcsr.c2073 env->siselect >= ISELECT_IMSIC_EIDELIVERY && in rmw_xireg()
/openbmc/qemu/hw/intc/
H A Driscv_imsic.c235 case ISELECT_IMSIC_EIDELIVERY: in riscv_imsic_rmw()