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Searched refs:GPR (Results 1 – 23 of 23) sorted by relevance

/openbmc/qemu/disas/
H A Dnanomips.c405 static const char *GPR(uint64 reg, Dis_info *info) in GPR() function
435 reg_list[counter + 1] = (char *)GPR(this_rt, info); in save_restore_list()
1479 const char *rt = GPR(rt_value, info); in ABSQ_S_PH()
1480 const char *rs = GPR(rs_value, info); in ABSQ_S_PH()
1501 const char *rt = GPR(rt_value, info); in ABSQ_S_QB()
1502 const char *rs = GPR(rs_value, info); in ABSQ_S_QB()
1523 const char *rt = GPR(rt_value, info); in ABSQ_S_W()
1524 const char *rs = GPR(rs_value, info); in ABSQ_S_W()
1545 const char *rs = GPR(rs_value, info); in ACLR()
1567 const char *rd = GPR(rd_value, info); in ADD()
[all …]
/openbmc/linux/sound/pci/emu10k1/
H A Demufx.c1790 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1792 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1794 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1796 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1798 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1802 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1804 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1808 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1865 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008); in _snd_emu10k1_init_efx()
1866 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008); in _snd_emu10k1_init_efx()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm920t/imx/
H A Dgeneric.c39 GPR(port) |= (1<<pin); in imx_gpio_mode()
41 GPR(port) &= ~(1<<pin); in imx_gpio_mode()
/openbmc/linux/arch/mips/alchemy/
H A DKconfig32 bool "Trapeze ITS GPR board"
/openbmc/linux/arch/powerpc/crypto/
H A Dchacha-p10le-8x.S50 .macro SAVE_GPR GPR OFFSET FRAME
51 std \GPR,\OFFSET(\FRAME)
64 .macro RESTORE_GPR GPR OFFSET FRAME
65 ld \GPR,\OFFSET(\FRAME)
H A Dpoly1305-p10le_64.S64 .macro SAVE_GPR GPR OFFSET FRAME
65 std \GPR,\OFFSET(\FRAME)
78 .macro RESTORE_GPR GPR OFFSET FRAME
79 ld \GPR,\OFFSET(\FRAME)
/openbmc/u-boot/doc/
H A DREADME.NDS3215 - 32 32-bit General Purpose Registers (GPR).
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-tqma8mq.dtsi235 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
240 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx27-pinctrl.txt24 Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
/openbmc/linux/include/uapi/sound/
H A Demu10k1.h157 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ macro
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dimx-weim.txt31 Purpose Register controller that contains WEIM CS GPR
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0001-FF-A-v15-arm64-smccc-add-support-for-SMCCCv1.2-x0-x1.patch55 + /* Save `res` and free a GPR that won't be clobbered */
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h125 #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) macro
/openbmc/linux/drivers/soc/qcom/
H A DKconfig264 tristate "Qualcomm APR/GPR Bus (Asynchronous/Generic Packet Router)"
/openbmc/linux/arch/arm/kernel/
H A Dentry-armv.S158 THUMB( add sp, r1 ) @ get SP in a GPR without
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h887 #define GPR(x) ((x) << 16) macro
H A Dni_dpm.c3362 GPR(ni_pi->cac_weights->gpr)); in ni_initialize_hardware_cac_manager()
/openbmc/qemu/target/hexagon/
H A DREADME208 runtime information for each thread and contains stuff like the GPR and
/openbmc/linux/arch/arc/
H A DKconfig375 (also referred to as r58:r59). These can also be used by gcc as GPR so
/openbmc/qemu/target/hexagon/imported/
H A Dcompare.idef56 /* Compare and put result in GPR */
/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.c.inc2018 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
2054 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
/openbmc/linux/Documentation/trace/
H A Dftrace.rst2788 type is smaller than a GPR, it is the responsibility of the consumer
2791 when using a u8 in a 64-bit GPR, bits [63:8] may contain arbitrary values,
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc687 * Vector registers uses the same 5 lower bits as GPR registers,