1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4# 5 6config ARC 7 def_bool y 8 select ARC_TIMERS 9 select ARCH_HAS_CACHE_LINE_SIZE 10 select ARCH_HAS_DEBUG_VM_PGTABLE 11 select ARCH_HAS_DMA_PREP_COHERENT 12 select ARCH_HAS_PTE_SPECIAL 13 select ARCH_HAS_SETUP_DMA_OPS 14 select ARCH_HAS_SYNC_DMA_FOR_CPU 15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC 17 select ARCH_32BIT_OFF_T 18 select BUILDTIME_TABLE_SORT 19 select CLONE_BACKWARDS 20 select COMMON_CLK 21 select DMA_DIRECT_REMAP 22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) 23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_PENDING_IRQ if SMP 27 select GENERIC_SCHED_CLOCK 28 select GENERIC_SMP_IDLE_THREAD 29 select GENERIC_IOREMAP 30 select GENERIC_STRNCPY_FROM_USER if MMU 31 select GENERIC_STRNLEN_USER if MMU 32 select HAVE_ARCH_KGDB 33 select HAVE_ARCH_TRACEHOOK 34 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 35 select HAVE_DEBUG_STACKOVERFLOW 36 select HAVE_DEBUG_KMEMLEAK 37 select HAVE_IOREMAP_PROT 38 select HAVE_KERNEL_GZIP 39 select HAVE_KERNEL_LZMA 40 select HAVE_KPROBES 41 select HAVE_KRETPROBES 42 select HAVE_REGS_AND_STACK_ACCESS_API 43 select HAVE_MOD_ARCH_SPECIFIC 44 select HAVE_PERF_EVENTS 45 select HAVE_SYSCALL_TRACEPOINTS 46 select IRQ_DOMAIN 47 select LOCK_MM_AND_FIND_VMA 48 select MODULES_USE_ELF_RELA 49 select OF 50 select OF_EARLY_FLATTREE 51 select PCI_SYSCALL if PCI 52 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING 53 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 54 select TRACE_IRQFLAGS_SUPPORT 55 56config LOCKDEP_SUPPORT 57 def_bool y 58 59config SCHED_OMIT_FRAME_POINTER 60 def_bool y 61 62config GENERIC_CSUM 63 def_bool y 64 65config ARCH_FLATMEM_ENABLE 66 def_bool y 67 68config MMU 69 def_bool y 70 71config NO_IOPORT_MAP 72 def_bool y 73 74config GENERIC_CALIBRATE_DELAY 75 def_bool y 76 77config GENERIC_HWEIGHT 78 def_bool y 79 80config STACKTRACE_SUPPORT 81 def_bool y 82 select STACKTRACE 83 84menu "ARC Architecture Configuration" 85 86menu "ARC Platform/SoC/Board" 87 88source "arch/arc/plat-tb10x/Kconfig" 89source "arch/arc/plat-axs10x/Kconfig" 90source "arch/arc/plat-hsdk/Kconfig" 91 92endmenu 93 94choice 95 prompt "ARC Instruction Set" 96 default ISA_ARCV2 97 98config ISA_ARCOMPACT 99 bool "ARCompact ISA" 100 select CPU_NO_EFFICIENT_FFS 101 help 102 The original ARC ISA of ARC600/700 cores 103 104config ISA_ARCV2 105 bool "ARC ISA v2" 106 select ARC_TIMERS_64BIT 107 help 108 ISA for the Next Generation ARC-HS cores 109 110endchoice 111 112menu "ARC CPU Configuration" 113 114choice 115 prompt "ARC Core" 116 default ARC_CPU_770 if ISA_ARCOMPACT 117 default ARC_CPU_HS if ISA_ARCV2 118 119config ARC_CPU_770 120 bool "ARC770" 121 depends on ISA_ARCOMPACT 122 select ARC_HAS_SWAPE 123 help 124 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 125 This core has a bunch of cool new features: 126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 127 Shared Address Spaces (for sharing TLB entries in MMU) 128 -Caches: New Prog Model, Region Flush 129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 130 131config ARC_CPU_HS 132 bool "ARC-HS" 133 depends on ISA_ARCV2 134 help 135 Support for ARC HS38x Cores based on ARCv2 ISA 136 The notable features are: 137 - SMP configurations of up to 4 cores with coherency 138 - Optional L2 Cache and IO-Coherency 139 - Revised Interrupt Architecture (multiple priorites, reg banks, 140 auto stack switch, auto regfile save/restore) 141 - MMUv4 (PIPT dcache, Huge Pages) 142 - Instructions for 143 * 64bit load/store: LDD, STD 144 * Hardware assisted divide/remainder: DIV, REM 145 * Function prologue/epilogue: ENTER_S, LEAVE_S 146 * IRQ enable/disable: CLRI, SETI 147 * pop count: FFS, FLS 148 * SETcc, BMSKN, XBFU... 149 150endchoice 151 152config ARC_TUNE_MCPU 153 string "Override default -mcpu compiler flag" 154 default "" 155 help 156 Override default -mcpu=xxx compiler flag (which is set depending on 157 the ISA version) with the specified value. 158 NOTE: If specified flag isn't supported by current compiler the 159 ISA default value will be used as a fallback. 160 161config CPU_BIG_ENDIAN 162 bool "Enable Big Endian Mode" 163 help 164 Build kernel for Big Endian Mode of ARC CPU 165 166config SMP 167 bool "Symmetric Multi-Processing" 168 select ARC_MCIP if ISA_ARCV2 169 help 170 This enables support for systems with more than one CPU. 171 172if SMP 173 174config NR_CPUS 175 int "Maximum number of CPUs (2-4096)" 176 range 2 4096 177 default "4" 178 179config ARC_SMP_HALT_ON_RESET 180 bool "Enable Halt-on-reset boot mode" 181 help 182 In SMP configuration cores can be configured as Halt-on-reset 183 or they could all start at same time. For Halt-on-reset, non 184 masters are parked until Master kicks them so they can start off 185 at designated entry point. For other case, all jump to common 186 entry point and spin wait for Master's signal. 187 188endif #SMP 189 190config ARC_MCIP 191 bool "ARConnect Multicore IP (MCIP) Support " 192 depends on ISA_ARCV2 193 default y if SMP 194 help 195 This IP block enables SMP in ARC-HS38 cores. 196 It provides for cross-core interrupts, multi-core debug 197 hardware semaphores, shared memory,.... 198 199menuconfig ARC_CACHE 200 bool "Enable Cache Support" 201 default y 202 203if ARC_CACHE 204 205config ARC_CACHE_LINE_SHIFT 206 int "Cache Line Length (as power of 2)" 207 range 5 7 208 default "6" 209 help 210 Starting with ARC700 4.9, Cache line length is configurable, 211 This option specifies "N", with Line-len = 2 power N 212 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 213 Linux only supports same line lengths for I and D caches. 214 215config ARC_HAS_ICACHE 216 bool "Use Instruction Cache" 217 default y 218 219config ARC_HAS_DCACHE 220 bool "Use Data Cache" 221 default y 222 223config ARC_CACHE_PAGES 224 bool "Per Page Cache Control" 225 default y 226 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 227 help 228 This can be used to over-ride the global I/D Cache Enable on a 229 per-page basis (but only for pages accessed via MMU such as 230 Kernel Virtual address or User Virtual Address) 231 TLB entries have a per-page Cache Enable Bit. 232 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 233 Global DISABLE + Per Page ENABLE won't work 234 235config ARC_CACHE_VIPT_ALIASING 236 bool "Support VIPT Aliasing D$" 237 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT 238 239endif #ARC_CACHE 240 241config ARC_HAS_ICCM 242 bool "Use ICCM" 243 help 244 Single Cycle RAMS to store Fast Path Code 245 246config ARC_ICCM_SZ 247 int "ICCM Size in KB" 248 default "64" 249 depends on ARC_HAS_ICCM 250 251config ARC_HAS_DCCM 252 bool "Use DCCM" 253 help 254 Single Cycle RAMS to store Fast Path Data 255 256config ARC_DCCM_SZ 257 int "DCCM Size in KB" 258 default "64" 259 depends on ARC_HAS_DCCM 260 261config ARC_DCCM_BASE 262 hex "DCCM map address" 263 default "0xA0000000" 264 depends on ARC_HAS_DCCM 265 266choice 267 prompt "MMU Version" 268 default ARC_MMU_V3 if ISA_ARCOMPACT 269 default ARC_MMU_V4 if ISA_ARCV2 270 271config ARC_MMU_V3 272 bool "MMU v3" 273 depends on ISA_ARCOMPACT 274 help 275 Introduced with ARC700 4.10: New Features 276 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 277 Shared Address Spaces (SASID) 278 279config ARC_MMU_V4 280 bool "MMU v4" 281 depends on ISA_ARCV2 282 283endchoice 284 285 286choice 287 prompt "MMU Page Size" 288 default ARC_PAGE_SIZE_8K 289 290config ARC_PAGE_SIZE_8K 291 bool "8KB" 292 help 293 Choose between 8k vs 16k 294 295config ARC_PAGE_SIZE_16K 296 bool "16KB" 297 298config ARC_PAGE_SIZE_4K 299 bool "4KB" 300 depends on ARC_MMU_V3 || ARC_MMU_V4 301 302endchoice 303 304choice 305 prompt "MMU Super Page Size" 306 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE 307 default ARC_HUGEPAGE_2M 308 309config ARC_HUGEPAGE_2M 310 bool "2MB" 311 312config ARC_HUGEPAGE_16M 313 bool "16MB" 314 315endchoice 316 317config PGTABLE_LEVELS 318 int "Number of Page table levels" 319 default 2 320 321config ARC_COMPACT_IRQ_LEVELS 322 depends on ISA_ARCOMPACT 323 bool "Setup Timer IRQ as high Priority" 324 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 325 depends on !SMP 326 327config ARC_FPU_SAVE_RESTORE 328 bool "Enable FPU state persistence across context switch" 329 help 330 ARCompact FPU has internal registers to assist with Double precision 331 Floating Point operations. There are control and stauts registers 332 for floating point exceptions and rounding modes. These are 333 preserved across task context switch when enabled. 334 335config ARC_CANT_LLSC 336 def_bool n 337 338config ARC_HAS_LLSC 339 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 340 default y 341 depends on !ARC_CANT_LLSC 342 343config ARC_HAS_SWAPE 344 bool "Insn: SWAPE (endian-swap)" 345 default y 346 347if ISA_ARCV2 348 349config ARC_USE_UNALIGNED_MEM_ACCESS 350 bool "Enable unaligned access in HW" 351 default y 352 select HAVE_EFFICIENT_UNALIGNED_ACCESS 353 help 354 The ARC HS architecture supports unaligned memory access 355 which is disabled by default. Enable unaligned access in 356 hardware and use software to use it 357 358config ARC_HAS_LL64 359 bool "Insn: 64bit LDD/STD" 360 help 361 Enable gcc to generate 64-bit load/store instructions 362 ISA mandates even/odd registers to allow encoding of two 363 dest operands with 2 possible source operands. 364 default y 365 366config ARC_HAS_DIV_REM 367 bool "Insn: div, divu, rem, remu" 368 default y 369 370config ARC_HAS_ACCL_REGS 371 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 372 default y 373 help 374 Depending on the configuration, CPU can contain accumulator reg-pair 375 (also referred to as r58:r59). These can also be used by gcc as GPR so 376 kernel needs to save/restore per process 377 378config ARC_DSP_HANDLED 379 def_bool n 380 381config ARC_DSP_SAVE_RESTORE_REGS 382 def_bool n 383 384choice 385 prompt "DSP support" 386 default ARC_DSP_NONE 387 help 388 Depending on the configuration, CPU can contain DSP registers 389 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). 390 Below are options describing how to handle these registers in 391 interrupt entry / exit and in context switch. 392 393config ARC_DSP_NONE 394 bool "No DSP extension presence in HW" 395 help 396 No DSP extension presence in HW 397 398config ARC_DSP_KERNEL 399 bool "DSP extension in HW, no support for userspace" 400 select ARC_HAS_ACCL_REGS 401 select ARC_DSP_HANDLED 402 help 403 DSP extension presence in HW, no support for DSP-enabled userspace 404 applications. We don't save / restore DSP registers and only do 405 some minimal preparations so userspace won't be able to break kernel 406 407config ARC_DSP_USERSPACE 408 bool "Support DSP for userspace apps" 409 select ARC_HAS_ACCL_REGS 410 select ARC_DSP_HANDLED 411 select ARC_DSP_SAVE_RESTORE_REGS 412 help 413 DSP extension presence in HW, support save / restore DSP registers to 414 run DSP-enabled userspace applications 415 416config ARC_DSP_AGU_USERSPACE 417 bool "Support DSP with AGU for userspace apps" 418 select ARC_HAS_ACCL_REGS 419 select ARC_DSP_HANDLED 420 select ARC_DSP_SAVE_RESTORE_REGS 421 help 422 DSP and AGU extensions presence in HW, support save / restore DSP 423 and AGU registers to run DSP-enabled userspace applications 424endchoice 425 426config ARC_IRQ_NO_AUTOSAVE 427 bool "Disable hardware autosave regfile on interrupts" 428 default n 429 help 430 On HS cores, taken interrupt auto saves the regfile on stack. 431 This is programmable and can be optionally disabled in which case 432 software INTERRUPT_PROLOGUE/EPILGUE do the needed work 433 434config ARC_LPB_DISABLE 435 bool "Disable loop buffer (LPB)" 436 help 437 On HS cores, loop buffer (LPB) is programmable in runtime and can 438 be optionally disabled. 439 440endif # ISA_ARCV2 441 442endmenu # "ARC CPU Configuration" 443 444config LINUX_LINK_BASE 445 hex "Kernel link address" 446 default "0x80000000" 447 help 448 ARC700 divides the 32 bit phy address space into two equal halves 449 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 450 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 451 Typically Linux kernel is linked at the start of untransalted addr, 452 hence the default value of 0x8zs. 453 However some customers have peripherals mapped at this addr, so 454 Linux needs to be scooted a bit. 455 If you don't know what the above means, leave this setting alone. 456 This needs to match memory start address specified in Device Tree 457 458config LINUX_RAM_BASE 459 hex "RAM base address" 460 default LINUX_LINK_BASE 461 help 462 By default Linux is linked at base of RAM. However in some special 463 cases (such as HSDK), Linux can't be linked at start of DDR, hence 464 this option. 465 466config HIGHMEM 467 bool "High Memory Support" 468 select HAVE_ARCH_PFN_VALID 469 select KMAP_LOCAL 470 help 471 With ARC 2G:2G address split, only upper 2G is directly addressable by 472 kernel. Enable this to potentially allow access to rest of 2G and PAE 473 in future 474 475config ARC_HAS_PAE40 476 bool "Support for the 40-bit Physical Address Extension" 477 depends on ISA_ARCV2 478 select HIGHMEM 479 select PHYS_ADDR_T_64BIT 480 help 481 Enable access to physical memory beyond 4G, only supported on 482 ARC cores with 40 bit Physical Addressing support 483 484config ARC_KVADDR_SIZE 485 int "Kernel Virtual Address Space size (MB)" 486 range 0 512 487 default "256" 488 help 489 The kernel address space is carved out of 256MB of translated address 490 space for catering to vmalloc, modules, pkmap, fixmap. This however may 491 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow 492 this to be stretched to 512 MB (by extending into the reserved 493 kernel-user gutter) 494 495config ARC_CURR_IN_REG 496 bool "cache current task pointer in gp" 497 default y 498 help 499 This reserves gp register to point to Current Task in 500 kernel mode eliding memory access for each access 501 502 503config ARC_EMUL_UNALIGNED 504 bool "Emulate unaligned memory access (userspace only)" 505 select SYSCTL_ARCH_UNALIGN_NO_WARN 506 select SYSCTL_ARCH_UNALIGN_ALLOW 507 depends on ISA_ARCOMPACT 508 help 509 This enables misaligned 16 & 32 bit memory access from user space. 510 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 511 potential bugs in code 512 513config HZ 514 int "Timer Frequency" 515 default 100 516 517config ARC_METAWARE_HLINK 518 bool "Support for Metaware debugger assisted Host access" 519 help 520 This options allows a Linux userland apps to directly access 521 host file system (open/creat/read/write etc) with help from 522 Metaware Debugger. This can come in handy for Linux-host communication 523 when there is no real usable peripheral such as EMAC. 524 525menuconfig ARC_DBG 526 bool "ARC debugging" 527 default y 528 529if ARC_DBG 530 531config ARC_DW2_UNWIND 532 bool "Enable DWARF specific kernel stack unwind" 533 default y 534 select KALLSYMS 535 help 536 Compiles the kernel with DWARF unwind information and can be used 537 to get stack backtraces. 538 539 If you say Y here the resulting kernel image will be slightly larger 540 but not slower, and it will give very useful debugging information. 541 If you don't debug the kernel, you can say N, but we may not be able 542 to solve problems without frame unwind information 543 544config ARC_DBG_JUMP_LABEL 545 bool "Paranoid checks in Static Keys (jump labels) code" 546 depends on JUMP_LABEL 547 default y if STATIC_KEYS_SELFTEST 548 help 549 Enable paranoid checks and self-test of both ARC-specific and generic 550 part of static keys (jump labels) related code. 551endif 552 553config ARC_BUILTIN_DTB_NAME 554 string "Built in DTB" 555 help 556 Set the name of the DTB to embed in the vmlinux binary 557 Leaving it blank selects the minimal "skeleton" dtb 558 559endmenu # "ARC Architecture Configuration" 560 561config ARCH_FORCE_MAX_ORDER 562 int "Maximum zone order" 563 default "11" if ARC_HUGEPAGE_16M 564 default "10" 565 566source "kernel/power/Kconfig" 567