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Searched refs:FIELD_EX32 (Results 1 – 25 of 80) sorted by relevance

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/openbmc/qemu/tests/qtest/
H A Dtpm-crb-test.c37 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceType), ==, 1); in tpm_crb_test()
38 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceVersion), ==, 1); in tpm_crb_test()
39 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapLocality), ==, 0); in tpm_crb_test()
40 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRBIdleBypass), ==, 0); in tpm_crb_test()
41 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapDataXferSizeSupport), in tpm_crb_test()
43 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapFIFO), ==, 0); in tpm_crb_test()
44 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, CapCRB), ==, 1); in tpm_crb_test()
45 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, InterfaceSelector), ==, 1); in tpm_crb_test()
46 g_assert_cmpint(FIELD_EX32(intfid, CRB_INTF_ID, RID), ==, 0); in tpm_crb_test()
53 g_assert_cmpint(FIELD_EX32(locstate, CRB_LOC_STATE, tpmEstablished), ==, 1); in tpm_crb_test()
[all …]
H A Dsifive-e-aon-watchdog-test.c107 g_assert(15 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE)); in test_wdogcfg()
108 g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN)); in test_wdogcfg()
109 g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP)); in test_wdogcfg()
110 g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); in test_wdogcfg()
111 g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE)); in test_wdogcfg()
112 g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, IP0)); in test_wdogcfg()
117 g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE)); in test_wdogcfg()
118 g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN)); in test_wdogcfg()
119 g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP)); in test_wdogcfg()
120 g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS)); in test_wdogcfg()
[all …]
/openbmc/qemu/target/arm/
H A Dcpu-features.h47 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; in isar_feature_aa32_thumb_div()
52 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; in isar_feature_aa32_arm_div()
58 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; in isar_feature_aa32_lob()
63 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; in isar_feature_aa32_jazelle()
68 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; in isar_feature_aa32_aes()
73 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; in isar_feature_aa32_pmull()
78 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; in isar_feature_aa32_sha1()
83 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; in isar_feature_aa32_sha2()
88 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; in isar_feature_aa32_crc32()
93 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; in isar_feature_aa32_rdm()
[all …]
/openbmc/qemu/target/loongarch/
H A Dtranslate.h18 #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
20 #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
21 #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
22 #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
23 #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
24 #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
25 #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
26 #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))
27 #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
/openbmc/qemu/hw/ssi/
H A Dibex_spi_host.c180 bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR); in ibex_spi_host_irq()
181 bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT); in ibex_spi_host_irq()
182 bool err_pending = FIELD_EX32(intr_state_reg, INTR_STATE, ERROR); in ibex_spi_host_irq()
183 bool status_pending = FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVENT); in ibex_spi_host_irq()
190 if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) { in ibex_spi_host_irq()
192 } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDBUSY) && in ibex_spi_host_irq()
193 FIELD_EX32(err_status_reg, ERROR_STATUS, CMDBUSY)) { in ibex_spi_host_irq()
196 } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDINVAL) && in ibex_spi_host_irq()
197 FIELD_EX32(err_status_reg, ERROR_STATUS, CMDINVAL)) { in ibex_spi_host_irq()
200 } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CSIDINVAL) && in ibex_spi_host_irq()
[all …]
/openbmc/qemu/hw/misc/
H A Dsifive_e_aon.c51 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 0 && in sifive_e_aon_wdt_update_wdogcount()
52 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 0) { in sifive_e_aon_wdt_update_wdogcount()
71 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE)); in sifive_e_aon_wdt_update_state()
75 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, ZEROCMP) == 1) { in sifive_e_aon_wdt_update_state()
82 if (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, RSTEN) == 1) { in sifive_e_aon_wdt_update_state()
88 qemu_set_irq(r->wdog_irq, FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, IP0)); in sifive_e_aon_wdt_update_state()
91 (FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS) == 1 || in sifive_e_aon_wdt_update_state()
92 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE) == 1)) { in sifive_e_aon_wdt_update_state()
95 FIELD_EX32(r->wdogcfg, AON_WDT_WDOGCFG, SCALE), in sifive_e_aon_wdt_update_state()
126 FIELD_EX32(r->wdogcfg, in sifive_e_aon_wdt_read()
[all …]
H A Dstm32l4x5_rcc.c425 val = FIELD_EX32(s->cr, CR, PLLSAI2ON); in rcc_update_cr_register()
434 val = FIELD_EX32(s->cr, CR, PLLSAI1ON); in rcc_update_cr_register()
446 val = FIELD_EX32(s->cr, CR, PLLON); in rcc_update_cr_register()
447 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) { in rcc_update_cr_register()
466 val = FIELD_EX32(s->cr, CR, HSEON); in rcc_update_cr_register()
467 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && in rcc_update_cr_register()
491 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 || in rcc_update_cr_register()
499 val = FIELD_EX32(s->cr, CR, HSION); in rcc_update_cr_register()
518 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 || in rcc_update_cr_register()
526 val = FIELD_EX32(s->cr, CR, MSION); in rcc_update_cr_register()
[all …]
H A Dxlnx-versal-trng.c317 if (FIELD_EX32(st, STATUS, CERTF) && FIELD_EX32(en, INT_CTRL, CERTF_EN)) { in trng_core_int_update()
321 if (FIELD_EX32(st, STATUS, DTF) && FIELD_EX32(en, INT_CTRL, DTF_EN)) { in trng_core_int_update()
325 if (FIELD_EX32(st, STATUS, DONE) && FIELD_EX32(en, INT_CTRL, DONE_EN)) { in trng_core_int_update()
339 if (FIELD_EX32(v32, INT_CTRL, CERTF_RST)) { in trng_int_ctrl_postw()
342 if (FIELD_EX32(v32, INT_CTRL, DTF_RST)) { in trng_int_ctrl_postw()
345 if (FIELD_EX32(v32, INT_CTRL, DONE_RST)) { in trng_int_ctrl_postw()
368 if (FIELD_EX32(events, STATUS, CERTF)) { in trng_fault_event_set()
379 if (FIELD_EX32(events, STATUS, DTF)) { in trng_fault_event_set()
405 if (FIELD_EX32(val64, CTRL, PRNGSRST)) { in trng_ctrl_postw()
411 if (!FIELD_EX32(val64, CTRL, PRNGSTART)) { in trng_ctrl_postw()
[all …]
H A Dimx6ul_ccm.c308 if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS], in imx6ul_analog_get_pll2_clk()
334 / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], in imx6ul_analog_get_pll2_pfd0_clk()
347 / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], in imx6ul_analog_get_pll2_pfd2_clk()
368 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) { in imx6ul_ccm_get_periph_clk2_sel_clk()
398 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_clk_sel_clk()
425 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF)); in imx6ul_ccm_get_periph_clk2_clk()
436 switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_sel_clk()
457 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF)); in imx6ul_ccm_get_ahb_clk()
469 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF)); in imx6ul_ccm_get_ipg_clk()
480 switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) { in imx6ul_ccm_get_per_sel_clk()
[all …]
H A Dbcm2835_cprman.c69 return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) in pll_is_locked()
70 && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); in pll_is_locked()
82 pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); in pll_update()
89 ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); in pll_update()
90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); in pll_update()
168 return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE) in pll_channel_is_enabled()
181 div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); in pll_channel_update()
259 return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE); in clock_mux_is_enabled()
265 uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC); in clock_mux_update()
314 if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) { in clock_mux_src_update()
[all …]
H A Dimx7_src.c187 if (FIELD_EX32(change_mask, CORE0, RST)) { in imx7_src_write()
191 if (FIELD_EX32(change_mask, CORE1, RST)) { in imx7_src_write()
207 if (FIELD_EX32(change_mask, CORE1, ENABLE)) { in imx7_src_write()
208 if (FIELD_EX32(current_value, CORE1, ENABLE)) { in imx7_src_write()
/openbmc/qemu/target/rx/
H A Dhelper.c29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); in rx_cpu_unpack_psw()
32 env->psw_pm = FIELD_EX32(psw, PSW, PM); in rx_cpu_unpack_psw()
34 env->psw_u = FIELD_EX32(psw, PSW, U); in rx_cpu_unpack_psw()
35 env->psw_i = FIELD_EX32(psw, PSW, I); in rx_cpu_unpack_psw()
37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; in rx_cpu_unpack_psw()
38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; in rx_cpu_unpack_psw()
39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); in rx_cpu_unpack_psw()
40 env->psw_c = FIELD_EX32(psw, PSW, C); in rx_cpu_unpack_psw()
H A Dop_helper.c67 if (!FIELD_EX32(env->fpsw, FPSW, E ## b)) { \
104 && !FIELD_EX32(env->fpsw, FPSW, DN)) { in update_fpsw()
109 if (FIELD_EX32(env->fpsw, FPSW, FLAGS) != 0) { in update_fpsw()
114 cause = FIELD_EX32(env->fpsw, FPSW, CAUSE); in update_fpsw()
115 enable = FIELD_EX32(env->fpsw, FPSW, ENABLE); in update_fpsw()
135 FIELD_DP32(fpsw, FPSW, FS, FIELD_EX32(fpsw, FPSW, FLAGS) != 0); in helper_set_fpsw()
137 set_float_rounding_mode(roundmode[FIELD_EX32(env->fpsw, FPSW, RM)], in helper_set_fpsw()
/openbmc/qemu/hw/rtc/
H A Dls7a_rtc.c102 return FIELD_EX32(s->cntrctl, RTC_CTRL, TOYEN) && in toy_enabled()
103 FIELD_EX32(s->cntrctl, RTC_CTRL, EO); in toy_enabled()
108 return FIELD_EX32(s->cntrctl, RTC_CTRL, RTCEN) && in rtc_enabled()
109 FIELD_EX32(s->cntrctl, RTC_CTRL, EO); in rtc_enabled()
128 tm->tm_sec = FIELD_EX32(val, TOY_MATCH, SEC); in toymatch_val_to_time()
129 tm->tm_min = FIELD_EX32(val, TOY_MATCH, MIN); in toymatch_val_to_time()
130 tm->tm_hour = FIELD_EX32(val, TOY_MATCH, HOUR); in toymatch_val_to_time()
131 tm->tm_mday = FIELD_EX32(val, TOY_MATCH, DAY); in toymatch_val_to_time()
132 tm->tm_mon = FIELD_EX32(val, TOY_MATCH, MON) - 1; in toymatch_val_to_time()
133 tm->tm_year += (FIELD_EX32(val, TOY_MATCH, YEAR) - (tm->tm_year & 0x3f)); in toymatch_val_to_time()
[all …]
/openbmc/qemu/hw/net/
H A Dcadence_gem.c429 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in tx_desc_get_buffer()
474 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in rx_desc_get_buffer()
484 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { in gem_get_desc_len()
560 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { in gem_get_max_buf_len()
570 size = FIELD_EX32(s->regs[R_NWCFG], in gem_get_max_buf_len()
666 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { in gem_can_receive()
811 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { in gem_mac_address_filter()
817 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { in gem_mac_address_filter()
825 if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || in gem_mac_address_filter()
826 (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { in gem_mac_address_filter()
[all …]
/openbmc/qemu/linux-user/arm/
H A Dtarget_proc.h26 midr_rev = FIELD_EX32(cpu->midr, MIDR_EL1, REVISION); in open_cpuinfo()
27 midr_part = FIELD_EX32(cpu->midr, MIDR_EL1, PARTNUM); in open_cpuinfo()
28 midr_var = FIELD_EX32(cpu->midr, MIDR_EL1, VARIANT); in open_cpuinfo()
29 midr_impl = FIELD_EX32(cpu->midr, MIDR_EL1, IMPLEMENTER); in open_cpuinfo()
/openbmc/qemu/hw/intc/
H A Dgic_internal.h135 #define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID))
136 #define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID))
137 #define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID))
138 #define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI))
139 #define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << 3)
140 #define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State))
141 #define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1))
142 #define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
/openbmc/qemu/target/riscv/
H A Dvector_internals.h36 return FIELD_EX32(simd_data(desc), VDATA, NF); in vext_nf()
73 return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); in vext_lmul()
78 return FIELD_EX32(simd_data(desc), VDATA, VM); in vext_vm()
83 return FIELD_EX32(simd_data(desc), VDATA, VMA); in vext_vma()
88 return FIELD_EX32(simd_data(desc), VDATA, VTA); in vext_vta()
93 return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); in vext_vta_all_1s()
H A Dtranslate.c1227 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); in riscv_tr_init_disas_context()
1228 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); in riscv_tr_init_disas_context()
1229 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); in riscv_tr_init_disas_context()
1230 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); in riscv_tr_init_disas_context()
1232 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); in riscv_tr_init_disas_context()
1236 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); in riscv_tr_init_disas_context()
1237 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); in riscv_tr_init_disas_context()
1238 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); in riscv_tr_init_disas_context()
1239 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; in riscv_tr_init_disas_context()
1240 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; in riscv_tr_init_disas_context()
[all …]
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c216 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); in stm32l4x5_usart_base_receive()
307 switch (FIELD_EX32(s->cr2, CR2, STOP)) { in stm32l4x5_update_params()
317 FIELD_EX32(s->cr2, CR2, STOP)); in stm32l4x5_update_params()
322 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { in stm32l4x5_update_params()
339 value = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_update_params()
346 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { in stm32l4x5_update_params()
423 retvalue = FIELD_EX32(s->brr, BRR, BRR); in stm32l4x5_usart_base_read()
443 retvalue = FIELD_EX32(s->rdr, RDR, RDR); in stm32l4x5_usart_base_read()
449 retvalue = FIELD_EX32(s->tdr, TDR, TDR); in stm32l4x5_usart_base_read()
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c824 multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + in canfd_msr_pre_write()
825 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + in canfd_msr_pre_write()
826 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); in canfd_msr_pre_write()
838 bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP); in canfd_msr_pre_write()
842 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { in canfd_msr_pre_write()
845 } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) { in canfd_msr_pre_write()
880 dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC); in regs2frame()
883 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, IDE)) { in regs2frame()
884 frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) | in regs2frame()
885 (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID_EXT)) | in regs2frame()
[all …]
H A Dxlnx-zynqmp-can.c391 frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC); in generate_frame()
393 frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3); in generate_frame()
394 frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2); in generate_frame()
395 frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1); in generate_frame()
396 frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0); in generate_frame()
398 frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7); in generate_frame()
399 frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6); in generate_frame()
400 frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5); in generate_frame()
401 frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4); in generate_frame()
547 FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN)); in can_srr_pre_write()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dmte_helper.c562 is_write = FIELD_EX32(desc, MTEDESC, WRITE); in mte_sync_check_fail()
596 int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_check_fail()
639 if (FIELD_EX32(desc, MTEDESC, WRITE)) { in mte_check_fail()
795 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in mte_probe_int()
796 type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; in mte_probe_int()
797 sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1); in mte_probe_int()
883 unsigned align = FIELD_EX32(desc, MTEDESC, ALIGN); in HELPER()
887 int idx = FIELD_EX32(desc, MTEDESC, MIDX); in HELPER()
888 bool w = FIELD_EX32(desc, MTEDESC, WRITE); in HELPER()
952 mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); in HELPER()
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/openbmc/qemu/hw/arm/
H A Draspi.c77 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_ram_size()
78 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); in board_ram_size()
83 int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); in board_processor_id()
85 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_processor_id()
107 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ in board_type()
108 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); in board_type()
323 FIELD_EX32(board_rev, REV_CODE, REVISION)); in raspi_machine_class_common_init()
/openbmc/qemu/hw/i2c/
H A Daspeed_i2c.c424 if (!FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, SRAM_EN) && dma_en) { in aspeed_i2c_check_sram()
597 FIELD_EX32(value, I2CM_INTR_STS, PKT_CMD_DONE)) { in aspeed_i2c_bus_new_write()
654 bus->regs[R_I2CM_DMA_TX_ADDR] = FIELD_EX32(value, I2CM_DMA_TX_ADDR, in aspeed_i2c_bus_new_write()
658 FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); in aspeed_i2c_bus_new_write()
663 bus->regs[R_I2CM_DMA_RX_ADDR] = FIELD_EX32(value, I2CM_DMA_RX_ADDR, in aspeed_i2c_bus_new_write()
667 FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); in aspeed_i2c_bus_new_write()
672 w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || in aspeed_i2c_bus_new_write()
673 FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T); in aspeed_i2c_bus_new_write()
679 if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) { in aspeed_i2c_bus_new_write()
681 FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN)); in aspeed_i2c_bus_new_write()
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