1*a55b9e72SHelge Deller /*
2*a55b9e72SHelge Deller * Arm specific proc functions for linux-user
3*a55b9e72SHelge Deller *
4*a55b9e72SHelge Deller * SPDX-License-Identifier: GPL-2.0-or-later
5*a55b9e72SHelge Deller */
6*a55b9e72SHelge Deller #ifndef ARM_TARGET_PROC_H
7*a55b9e72SHelge Deller #define ARM_TARGET_PROC_H
8*a55b9e72SHelge Deller
open_cpuinfo(CPUArchState * cpu_env,int fd)9*a55b9e72SHelge Deller static int open_cpuinfo(CPUArchState *cpu_env, int fd)
10*a55b9e72SHelge Deller {
11*a55b9e72SHelge Deller ARMCPU *cpu = env_archcpu(cpu_env);
12*a55b9e72SHelge Deller int arch, midr_rev, midr_part, midr_var, midr_impl;
13*a55b9e72SHelge Deller target_ulong elf_hwcap = get_elf_hwcap();
14*a55b9e72SHelge Deller target_ulong elf_hwcap2 = get_elf_hwcap2();
15*a55b9e72SHelge Deller const char *elf_name;
16*a55b9e72SHelge Deller int num_cpus, len_part, len_var;
17*a55b9e72SHelge Deller
18*a55b9e72SHelge Deller #if TARGET_BIG_ENDIAN
19*a55b9e72SHelge Deller # define END_SUFFIX "b"
20*a55b9e72SHelge Deller #else
21*a55b9e72SHelge Deller # define END_SUFFIX "l"
22*a55b9e72SHelge Deller #endif
23*a55b9e72SHelge Deller
24*a55b9e72SHelge Deller arch = 8;
25*a55b9e72SHelge Deller elf_name = "v8" END_SUFFIX;
26*a55b9e72SHelge Deller midr_rev = FIELD_EX32(cpu->midr, MIDR_EL1, REVISION);
27*a55b9e72SHelge Deller midr_part = FIELD_EX32(cpu->midr, MIDR_EL1, PARTNUM);
28*a55b9e72SHelge Deller midr_var = FIELD_EX32(cpu->midr, MIDR_EL1, VARIANT);
29*a55b9e72SHelge Deller midr_impl = FIELD_EX32(cpu->midr, MIDR_EL1, IMPLEMENTER);
30*a55b9e72SHelge Deller len_part = 3;
31*a55b9e72SHelge Deller len_var = 1;
32*a55b9e72SHelge Deller
33*a55b9e72SHelge Deller #ifndef TARGET_AARCH64
34*a55b9e72SHelge Deller /* For simplicity, treat ARMv8 as an arm64 kernel with CONFIG_COMPAT. */
35*a55b9e72SHelge Deller if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
36*a55b9e72SHelge Deller if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
37*a55b9e72SHelge Deller arch = 7;
38*a55b9e72SHelge Deller midr_var = (cpu->midr >> 16) & 0x7f;
39*a55b9e72SHelge Deller len_var = 2;
40*a55b9e72SHelge Deller if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
41*a55b9e72SHelge Deller elf_name = "armv7m" END_SUFFIX;
42*a55b9e72SHelge Deller } else {
43*a55b9e72SHelge Deller elf_name = "armv7" END_SUFFIX;
44*a55b9e72SHelge Deller }
45*a55b9e72SHelge Deller } else {
46*a55b9e72SHelge Deller midr_part = cpu->midr >> 4;
47*a55b9e72SHelge Deller len_part = 7;
48*a55b9e72SHelge Deller if (arm_feature(&cpu->env, ARM_FEATURE_V6)) {
49*a55b9e72SHelge Deller arch = 6;
50*a55b9e72SHelge Deller elf_name = "armv6" END_SUFFIX;
51*a55b9e72SHelge Deller } else if (arm_feature(&cpu->env, ARM_FEATURE_V5)) {
52*a55b9e72SHelge Deller arch = 5;
53*a55b9e72SHelge Deller elf_name = "armv5t" END_SUFFIX;
54*a55b9e72SHelge Deller } else {
55*a55b9e72SHelge Deller arch = 4;
56*a55b9e72SHelge Deller elf_name = "armv4" END_SUFFIX;
57*a55b9e72SHelge Deller }
58*a55b9e72SHelge Deller }
59*a55b9e72SHelge Deller }
60*a55b9e72SHelge Deller #endif
61*a55b9e72SHelge Deller
62*a55b9e72SHelge Deller #undef END_SUFFIX
63*a55b9e72SHelge Deller
64*a55b9e72SHelge Deller num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
65*a55b9e72SHelge Deller for (int i = 0; i < num_cpus; i++) {
66*a55b9e72SHelge Deller dprintf(fd,
67*a55b9e72SHelge Deller "processor\t: %d\n"
68*a55b9e72SHelge Deller "model name\t: ARMv%d Processor rev %d (%s)\n"
69*a55b9e72SHelge Deller "BogoMIPS\t: 100.00\n"
70*a55b9e72SHelge Deller "Features\t:",
71*a55b9e72SHelge Deller i, arch, midr_rev, elf_name);
72*a55b9e72SHelge Deller
73*a55b9e72SHelge Deller for (target_ulong j = elf_hwcap; j ; j &= j - 1) {
74*a55b9e72SHelge Deller dprintf(fd, " %s", elf_hwcap_str(ctz64(j)));
75*a55b9e72SHelge Deller }
76*a55b9e72SHelge Deller for (target_ulong j = elf_hwcap2; j ; j &= j - 1) {
77*a55b9e72SHelge Deller dprintf(fd, " %s", elf_hwcap2_str(ctz64(j)));
78*a55b9e72SHelge Deller }
79*a55b9e72SHelge Deller
80*a55b9e72SHelge Deller dprintf(fd, "\n"
81*a55b9e72SHelge Deller "CPU implementer\t: 0x%02x\n"
82*a55b9e72SHelge Deller "CPU architecture: %d\n"
83*a55b9e72SHelge Deller "CPU variant\t: 0x%0*x\n",
84*a55b9e72SHelge Deller midr_impl, arch, len_var, midr_var);
85*a55b9e72SHelge Deller if (arch >= 7) {
86*a55b9e72SHelge Deller dprintf(fd, "CPU part\t: 0x%0*x\n", len_part, midr_part);
87*a55b9e72SHelge Deller }
88*a55b9e72SHelge Deller dprintf(fd, "CPU revision\t: %d\n\n", midr_rev);
89*a55b9e72SHelge Deller }
90*a55b9e72SHelge Deller
91*a55b9e72SHelge Deller if (arch < 8) {
92*a55b9e72SHelge Deller dprintf(fd, "Hardware\t: QEMU v%s %s\n", QEMU_VERSION,
93*a55b9e72SHelge Deller cpu->dtb_compatible ? : "");
94*a55b9e72SHelge Deller dprintf(fd, "Revision\t: 0000\n");
95*a55b9e72SHelge Deller dprintf(fd, "Serial\t\t: 0000000000000000\n");
96*a55b9e72SHelge Deller }
97*a55b9e72SHelge Deller return 0;
98*a55b9e72SHelge Deller }
99*a55b9e72SHelge Deller #define HAVE_ARCH_PROC_CPUINFO
100*a55b9e72SHelge Deller
101*a55b9e72SHelge Deller #endif /* ARM_TARGET_PROC_H */
102