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Searched refs:DCSR (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddcsr.txt2 Debug Control and Status Register (DCSR) Binding
16 defined DCSR Memory Map. Child nodes will describe the individual
25 The DCSR space exists in the memory-mapped bus.
44 range of the DCSR space.
57 This node represents the region of DCSR space allocated to the EPU
91 offset and length of the DCSR space registers of the device
107 This node represents the region of DCSR space allocated to the NPC
120 offset and length of the DCSR space registers of the device
122 The Nexus Port controller occupies two regions in the DCSR space
144 This node represents the region of DCSR space allocated to the NXC
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/openbmc/u-boot/board/keymile/kmp204x/
H A Dpbi.cfg9 #Configure ALTCBAR for DCSR -> DCSR@89000000
/openbmc/linux/drivers/dma/
H A Dpxa_dma.c27 #define DCSR(n) (0x0000 + ((n) << 2)) macro
271 dcsr = _phy_readl_relaxed(phy, DCSR); in chan_state_show()
437 dcsr = phy_readl_relaxed(phy, DCSR); in is_chan_running()
476 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR); in phy_enable()
486 dcsr = phy_readl_relaxed(phy, DCSR); in phy_disable()
489 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); in phy_disable()
593 dcsr = phy_readl_relaxed(phy, DCSR); in clear_chan_irq()
594 phy_writel(phy, dcsr, DCSR); in clear_chan_irq()
649 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR); in pxad_chan_handler()
H A Dmmp_pdma.c24 #define DCSR 0x0000 macro
168 reg = (phy->idx << 2) + DCSR; in enable_chan()
179 reg = (phy->idx << 2) + DCSR; in disable_chan()
187 u32 reg = (phy->idx << 2) + DCSR; in clear_chan_irq()
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DREADME44 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/board/freescale/ls1043aqds/
H A DREADME52 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME52 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME48 0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME106 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME107 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
/openbmc/u-boot/doc/
H A DREADME.b4860qds188 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
218 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME110 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/board/freescale/t4qds/
H A DREADME108 0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME99 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME134 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME178 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME138 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME165 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h131 #define DCSR(x) (0x40000000 | ((x) << 2)) macro