1877bfe37SValentin Longchamp# SPDX-License-Identifier: GPL-2.0+ 2877bfe37SValentin Longchamp# 3*83d290c5STom Rini# Copyright 2012 Freescale Semiconductor, Inc. 4877bfe37SValentin Longchamp# Refer docs/README.pblimage for more details about how-to configure 5877bfe37SValentin Longchamp# and create PBL boot image 6877bfe37SValentin Longchamp# 7877bfe37SValentin Longchamp 8877bfe37SValentin Longchamp#PBI commands 92846c43eSValentin Longchamp#Configure ALTCBAR for DCSR -> DCSR@89000000 102846c43eSValentin Longchamp091380c0 000009C4 11fabb9297SValentin Longchamp09000010 00000000 122846c43eSValentin Longchamp091380c0 000009C4 13fabb9297SValentin Longchamp09000014 00000000 142846c43eSValentin Longchamp091380c0 000009C4 15fabb9297SValentin Longchamp09000018 81d00000 162846c43eSValentin Longchamp#Workaround for A-004849 172846c43eSValentin Longchamp091380c0 000009C4 182846c43eSValentin Longchamp890B0050 00000002 192846c43eSValentin Longchamp091380c0 000009C4 202846c43eSValentin Longchamp890B0054 00000002 212846c43eSValentin Longchamp091380c0 000009C4 222846c43eSValentin Longchamp890B0058 00000002 232846c43eSValentin Longchamp091380c0 000009C4 242846c43eSValentin Longchamp890B005C 00000002 252846c43eSValentin Longchamp091380c0 000009C4 262846c43eSValentin Longchamp890B0090 00000002 272846c43eSValentin Longchamp091380c0 000009C4 282846c43eSValentin Longchamp890B0094 00000002 292846c43eSValentin Longchamp091380c0 000009C4 302846c43eSValentin Longchamp890B0098 00000002 312846c43eSValentin Longchamp091380c0 000009C4 322846c43eSValentin Longchamp890B009C 00000002 332846c43eSValentin Longchamp091380c0 000009C4 342846c43eSValentin Longchamp890B0108 00000012 352846c43eSValentin Longchamp091380c0 000009C4 362846c43eSValentin Longchamp#Workaround for A-006559 needed for rev 2.0 of P2041 silicon 372846c43eSValentin Longchamp89021008 0000f000 382846c43eSValentin Longchamp091380c0 000009C4 392846c43eSValentin Longchamp89021028 0000f000 402846c43eSValentin Longchamp091380c0 000009C4 412846c43eSValentin Longchamp89021048 0000f000 422846c43eSValentin Longchamp091380c0 000009C4 432846c43eSValentin Longchamp89021068 0000f000 442846c43eSValentin Longchamp091380c0 000009C4 452846c43eSValentin Longchamp#Flush PBL data 462846c43eSValentin Longchamp09138000 00000000 472846c43eSValentin Longchamp#Disable ALTCBAR 48fabb9297SValentin Longchamp09000018 00000000 492846c43eSValentin Longchamp091380c0 000009C4 50877bfe37SValentin Longchamp#Initialize CPC1 as 1MB SRAM 51877bfe37SValentin Longchamp09010000 00200400 52877bfe37SValentin Longchamp09138000 00000000 53877bfe37SValentin Longchamp091380c0 00000100 54877bfe37SValentin Longchamp09010100 00000000 55877bfe37SValentin Longchamp09010104 fff0000b 56877bfe37SValentin Longchamp09010f00 08000000 57877bfe37SValentin Longchamp09010000 80000000 58877bfe37SValentin Longchamp#Configure LAW for CPC1 59877bfe37SValentin Longchamp09000d00 00000000 60877bfe37SValentin Longchamp09000d04 fff00000 61877bfe37SValentin Longchamp09000d08 81000013 62877bfe37SValentin Longchamp09000010 00000000 63877bfe37SValentin Longchamp09000014 ff000000 64877bfe37SValentin Longchamp09000018 81000000 65877bfe37SValentin Longchamp#Initialize eSPI controller, default configuration is slow for eSPI to 66877bfe37SValentin Longchamp#load data, this configuration comes from u-boot eSPI driver. 67877bfe37SValentin Longchamp09110000 80000403 68877bfe37SValentin Longchamp09110020 27170008 69877bfe37SValentin Longchamp09110024 00100008 70877bfe37SValentin Longchamp09110028 00100008 71877bfe37SValentin Longchamp0911002c 00100008 72877bfe37SValentin Longchamp#Flush PBL data 73877bfe37SValentin Longchamp09138000 00000000 74877bfe37SValentin Longchamp091380c0 00000000 75