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/openbmc/linux/Documentation/kbuild/
H A DKconfig.recursion-issue-0113 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
30 # what values are possible for CORE we ended up needing to address questions
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
38 # of the "select CORE" from CORE_BELL_A_ADVANCED as that is implicit already
39 # since CORE_BELL_A depends on CORE. Recursive dependency issues are not always
[all …]
H A DKconfig.recursion-issue-0225 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
63 select CORE
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_init.h87 { MT_BBP(CORE, 1), 0x00000002 },
88 { MT_BBP(CORE, 4), 0x00000000 },
89 { MT_BBP(CORE, 24), 0x00000000 },
90 { MT_BBP(CORE, 32), 0x4003000a },
91 { MT_BBP(CORE, 42), 0x00000000 },
92 { MT_BBP(CORE, 44), 0x00000000 },
H A Dphy.c191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
518 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
526 mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); in mt76x0_phy_tssi_dc_calibrate()
527 dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
536 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
552 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { in mt76x0_phy_tssi_adc_calibrate()
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
H A Dusb_mac.c143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
H A Dpci_phy.c83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds146 SW3=XX00XXXX == CORE:CCB 2:1
147 XX01XXXX == CORE:CCB 5:2
148 XX10XXXX == CORE:CCB 3:1
149 XX11XXXX == CORE:CCB 7:2
176 SW3=X000XXXX == CORE:CCB 4:1
177 X001XXXX == CORE:CCB 9:2
178 X010XXXX == CORE:CCB 1:1
179 X011XXXX == CORE:CCB 3:2
180 X100XXXX == CORE:CCB 2:1
181 X101XXXX == CORE:CCB 5:2
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A DMakefile.softmmu-target5 CORE=dc232b
6 ifneq ($(shell $(QEMU) -cpu help | grep -w $(CORE)),)
19 QEMU_OPTS+=-M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel
21 INCLUDE_DIRS = $(SRC_PATH)/target/xtensa/core-$(CORE)
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro5-epcore.dts3 * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE)
14 model = "UniPhier Pro5 EP-CORE Board";
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME24 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
25 01100 :: CORE = 2.5:1
26 10000 :: CORE = 3:1
27 11100 :: CORE = 3.5:1
28 10100 :: CORE = 4:1
29 01110 :: CORE = 4.5:1
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-protocols/net-snmp/net-snmp/
H A D0007-configure-fix-incorrect-variable.patch23 …(MAKE) LD_RUN_PATH="$(libdir):`$(PERL) -e 'use Config; print qq($$Config{archlibexp}/CORE);'`") ; \
24 …E) LD_RUN_PATH="$(libdir):`$(PERL) -e 'use Config; print qq($$Config{installprivlib}/CORE);'`") ; \
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dchip_registers.h9 #define CORE 0x000000000000 macro
10 #define CCE (CORE + 0x000000000000)
11 #define ASIC (CORE + 0x000000400000)
12 #define MISC (CORE + 0x000000500000)
13 #define DC_TOP_CSRS (CORE + 0x000000600000)
14 #define CHIP_DEBUG (CORE + 0x000000700000)
15 #define RXE (CORE + 0x000001000000)
16 #define TXE (CORE + 0x000001800000)
/openbmc/linux/drivers/cpufreq/
H A Dimx-cpufreq-dt.c39 CORE, enumerator
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
/openbmc/openbmc/poky/scripts/lib/checklayer/cases/
H A Dcommon.py15 if self.tc.layer['type'] == LayerType.CORE:
66 if self.tc.layer["type"] == LayerType.CORE:
H A Ddistro.py14 if self.tc.layer['type'] not in (LayerType.DISTRO, LayerType.CORE):
/openbmc/openbmc/poky/meta/recipes-devtools/perl/
H A Dperl_5.40.0.bb150 dir=$(echo ${D}/${libdir}/perl5/${PV}/*/CORE)
167 …}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/config.h ${D}${libdir}/perl5/${PV}/${TARGET_ARCH}…
211 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/config.h \
212 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/xconfig.h \
213 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/perl.h \
214 ${PKGD}${libdir}/perl5/${PV}/${TARGET_ARCH}-linux/CORE/pp.h \
280 FILES:${PN}-staticdev:append = " ${libdir}/perl5/${PV}/*/CORE/libperl.a"
282 FILES:${PN}-dev:append = " ${libdir}/perl5/${PV}/*/CORE"
/openbmc/openbmc/poky/meta/recipes-kernel/perf/
H A Dperf-perl.inc5 …RL_INC = "${STAGING_LIBDIR}${PERL_OWN_DIR}/perl5/${@get_perl_version(d)}/${@get_perl_arch(d)}/CORE"
/openbmc/u-boot/include/power/
H A Dtps65910.h12 #define CORE 1 macro
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-core-thermal.dtsi3 * Device Tree Source for OMAP543x SoC CORE thermal
/openbmc/u-boot/arch/arm/dts/
H A Domap5-core-thermal.dtsi2 * Device Tree Source for OMAP543x SoC CORE thermal
/openbmc/u-boot/board/siemens/pxm2/
H A Dboard.c89 #define CORE 1 macro
156 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { in spl_siemens_board_init()
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrcc57d.c18 u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crcc57d_set_src()
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S147 @ Enable CORE Soft Reset
167 @ Disable CORE soft reset

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