Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_IMMR (Results 1 – 25 of 155) sorted by relevance

1234567

/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h14 #define CONFIG_SYS_IMMR 0x01000000 macro
20 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
21 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
22 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
23 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
24 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
26 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
27 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
28 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000 macro
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
25 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
[all …]
H A Dimmap_lsch2.h11 #define CONFIG_SYS_IMMR 0x01000000 macro
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
22 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
23 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Diopin_8xx.h30 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_high()
53 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_low()
76 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_is_high()
100 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_is_low()
124 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_out()
147 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_in()
170 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_is_out()
194 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_is_in()
218 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_odr()
233 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in iopin_set_act()
[all …]
H A Dimmap_85xx.h2944 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2946 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2948 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2950 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
2952 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
2954 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2956 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2958 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2960 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2962 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
[all …]
/openbmc/u-boot/board/ids/ids8313/
H A Dids8313.c53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram()
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init()
161 duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; in misc_init_r()
162 duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; in misc_init_r()
164 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; in misc_init_r()
192 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; in spi_cs_activate()
203 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; in spi_cs_deactivate()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dinterrupts.c34 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in interrupt_init_cpu()
52 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in external_interrupt()
108 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in cpm_interrupt()
148 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in irq_install_handler()
172 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in irq_free_handler()
192 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in cpm_interrupt_init()
227 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; in timer_interrupt_cpu()
H A Dcpu.c38 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in check_CPU()
105 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in checkicache()
146 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in checkdcache()
182 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in upmconfig()
198 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in do_reset()
239 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; in get_tbclk()
/openbmc/u-boot/include/configs/
H A DMPC8315ERDB.h80 #define CONFIG_SYS_IMMR 0xE0000000 macro
284 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
285 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
362 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
364 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
389 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
393 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
466 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
470 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
H A Dmpc8308_p1m.h101 #define CONFIG_SYS_IMMR 0xE0000000 macro
290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
330 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
332 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
410 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
412 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
H A DTQM834x.h22 #define CONFIG_SYS_IMMR 0xff400000 macro
156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
183 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
185 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
376 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
380 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
H A DMPC837XEMDS.h102 #define CONFIG_SYS_IMMR 0xE0000000 macro
306 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
307 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
382 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
384 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
416 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
420 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
510 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
514 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
H A DMPC8308RDB.h98 #define CONFIG_SYS_IMMR 0xE0000000 macro
300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
362 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
364 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
443 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
445 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
H A Dvme8349.h55 #define CONFIG_SYS_IMMR 0xE0000000 macro
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
217 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
219 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
440 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
442 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
H A Dsbc8349.h49 #define CONFIG_SYS_IMMR 0xE0000000 macro
265 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
266 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
282 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
284 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
543 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
547 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
H A DMPC837XERDB.h108 #define CONFIG_SYS_IMMR 0xE0000000 macro
325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
430 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
434 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
525 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
529 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
H A DMPC8349EMDS.h43 #define CONFIG_SYS_IMMR 0xE0000000 macro
309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
333 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
335 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
630 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
634 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
/openbmc/u-boot/board/freescale/mpc8313erdb/
H A Dmpc8313erdb.c26 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in board_early_init_f()
77 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; in pci_init_board()
132 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), in board_init_f()
152 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); in putc()
154 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); in putc()
/openbmc/u-boot/drivers/gpio/
H A Dmpc83xx_gpio.c53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_input()
73 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_output()
101 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_get_value()
120 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_set_value()
151 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in mpc83xx_gpio_init_f()
/openbmc/u-boot/include/configs/km/
H A Dkm83xx-common.h24 #define CONFIG_SYS_IMMR 0xE0000000 macro
129 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
130 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
232 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
234 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
/openbmc/u-boot/drivers/spi/
H A Dsoft_spi_legacy.c67 #ifdef CONFIG_SYS_IMMR in spi_claim_bus()
68 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in spi_claim_bus()
104 #ifdef CONFIG_SYS_IMMR in spi_xfer()
105 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in spi_xfer()
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A Dmpc8315erdb.c25 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in board_early_init_f()
119 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; in pci_init_board()
220 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), in board_init_f()
240 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); in putc()
242 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); in putc()
/openbmc/u-boot/board/freescale/mpc837xemds/
H A Dmpc837xemds.c34 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in board_early_init_f()
65 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in board_mmc_init()
88 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in board_eth_init()
187 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in ft_tsec_fixup()
222 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init()
251 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram()
298 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; in board_pci_host_broken()
/openbmc/u-boot/board/freescale/mpc8308rdb/
H A Dmpc8308rdb.c36 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in spi_cs_activate()
44 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in spi_cs_deactivate()
106 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in pci_init_board()
132 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; in misc_init_r()
/openbmc/u-boot/board/ve8313/
H A Dve8313.c37 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in fixed_sdram()
92 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in dram_init()
118 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in board_early_init_f()
137 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; in hw_watchdog_reset()
174 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; in pci_init_board()

1234567