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Searched refs:CCR (Results 1 – 25 of 54) sorted by relevance

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/openbmc/linux/arch/arm/mach-omap1/
H A Domap-dma.c158 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
162 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
200 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
203 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
268 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
271 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
418 p->dma_write(dev_id | (1 << 10), CCR, free_ch); in omap_request_dma()
420 p->dma_write(dev_id, CCR, free_ch); in omap_request_dma()
443 p->dma_write(0, CCR, lch); in omap_free_dma()
510 l = p->dma_read(CCR, lch); in omap_start_dma()
[all …]
H A Ddma.c57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
/openbmc/linux/drivers/dma/
H A Dtxx9dmac.h77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
H A Dtxx9dmac.c295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
/openbmc/u-boot/arch/sh/cpu/sh4/
H A Dcache.c42 ccr = inl(CCR); in cache_control()
48 outl(CCR_CACHE_STOP, CCR); in cache_control()
50 outl(CCR_CACHE_INIT, CCR); in cache_control()
/openbmc/linux/arch/arm/mach-imx/
H A Dpm-imx6.c31 #define CCR 0x0 macro
255 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
258 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
261 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
264 writel(val, ccm_base + CCR); in imx6_enable_rbc()
288 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
291 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/openbmc/u-boot/doc/
H A DREADME.ne20003 that the CCR is correctly initialized.
26 - Address of the CCR (card configuration register). It could be found
32 - The value to be written in the CCR. It selects among different I/O
/openbmc/linux/drivers/clocksource/
H A Dtimer-atmel-tcb.c104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7763.h11 #define CCR 0xFF00001C macro
H A Dcpu_sh7269.h6 #define CCR CCR1 macro
H A Dcpu_sh7264.h6 #define CCR CCR1 macro
H A Dcpu_sh7203.h6 #define CCR CCR1 macro
H A Dcpu_sh7706.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7710.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7734.h11 #define CCR 0xFF00001C macro
H A Dcpu_sh7750.h28 #define CCR 0xFF00001C macro
H A Dcpu_sh7785.h20 #define CCR 0xFF00001C macro
H A Dcpu_sh7723.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7724.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7757.h9 #define CCR 0xFF00001C macro
/openbmc/linux/drivers/pwm/
H A Dpwm-atmel-tcb.c166 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
171 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
253 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
520 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
/openbmc/linux/include/sound/
H A Demu10k1.h475 #define CCR 0x09 /* Cache control register */ macro
476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
/openbmc/linux/drivers/counter/
H A Dmicrochip-tcb-capture.c130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
137 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
/openbmc/u-boot/board/ms7750se/
H A Dlowlevel_init.S100 CCR_A: .long CCR
/openbmc/linux/Documentation/translations/zh_CN/arch/parisc/
H A Dregisters.rst28 CR10 (CCR) FPU延迟保存*

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